Results 1 to 10 of about 11,636 (194)

Hardware Trojan Mitigation Technique in Network-on-Chip (NoC). [PDF]

open access: yesMicromachines (Basel), 2023
Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits.
Hussain M   +6 more
europepmc   +5 more sources

PaCHNOC: Packet and Circuit Hybrid Switching NoC for Real-Time Parallel Stream Signal Processing [PDF]

open access: yesMicromachines
Real-time heterogeneous parallel embedded digital signal processor (DSP) systems process multiple data streams in parallel in a stringent time interval. This type of system on chip (SoC) requires the network on chip (NoC) to establish multiple symbiotic ...
Peng Hao   +4 more
doaj   +2 more sources

A novel buffering fault‐tolerance approach for network on chip (NoC)

open access: yesIET Circuits, Devices and Systems, 2023
Network‐on‐Chip (NoC) is a key component in chip multiprocessors (CMPs) as it supports communication between many cores. NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC ...
Nima Jafarzadeh   +7 more
doaj   +2 more sources

PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs [PDF]

open access: yesMicromachines, 2023
Hundreds of processor cores or modules are integrated into a single chip. The traditional bus or crossbar is challenged by bandwidth, scalability, and silicon area, and cannot meet the requirements of high end applications.
Xinbing Zhou, Peng Hao, Dake Liu
doaj   +2 more sources

Data of multilayer mesh NoC performance analysis for throughput and delay over FTP and CBR applications [PDF]

open access: yesData in Brief, 2022
This work demonstrates the Network on Chip(NoC) performance evaluation parameters matrix-like throughput and latency of multilayer NoC Mesh topology for random break-in links(0,5,10,15,20%) over constant bit rate (CBR) and file transfer protocol (FTP ...
Charanarur Panem   +2 more
doaj   +2 more sources

An Adaptive Routing Algorithm for Wireless Network on Chips [PDF]

open access: yesJournal of Electrical and Computer Engineering Innovations, 2022
Background and Objectives: Wireless Network on Chip (WNoC) is one of the promising interconnection architectures for future many-core processors. Besides the architectures and topologies of these WNoCs, designing an efficient routing algorithm that uses ...
A. Tajary, E. Tahanian
doaj   +1 more source

Review of Network on Chip Routing Algorithms [PDF]

open access: yesEAI Endorsed Transactions on Context-aware Systems and Applications, 2020
System on chip (SoC) is an integrated circuit in which components are communicating through the bus interconnection system. Network on chip (NoC) is a communication network for a multiprocessor system on chip (MPSoC).
Khurshid Ahmad, Muhammad Sethi
doaj   +1 more source

An enhanced approach towards improving the performance of embedding memory management units into Network-on-Chip

open access: yese-Prime: Advances in Electrical Engineering, Electronics and Energy, 2023
Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large delay ...
Debasis Behera   +3 more
doaj   +1 more source

A Scalable Software Defined Network Orchestrator for Photonic Network on Chips

open access: yesIEEE Access, 2021
Photonic networks and software-defined networks are two promising technologies to improve network-on-chips performance, scalability, and resource utilization.
Doaa A. Hamdi   +3 more
doaj   +1 more source

Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures

open access: yesIEEE Access, 2023
Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures.
Lashmi Kondoth   +3 more
doaj   +1 more source

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