Results 11 to 20 of about 1,082 (135)
Automatika, 2023 Systems-on-chips need numerous predesigned cores to advance. NoC enables Multi-Core SoCs (MC_SoCs). Conventional NoC cores use power and latency on multi-hop wired connections.
Dinesh Kumar T.R., Karthikeyan A.
doaj +1 more source
Enhanced overloaded code division multiple access for network on chip
IET Computers & Digital Techniques, 2022 The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On
Behnam Vakili, Morteza Gholipour
doaj +1 more source
Application Mapping Using Cuckoo Search Optimization With Lévy Flight for NoC-Based System
IEEE Access, 2021 Network on chip (NoC) is a promising communication infrastructure for multiple cores on a chip to exchange data efficiently. In such NoC architecture, application mapping is a process of assigning tasks to the processing cores.
Muhammad Junaid Mohiz +5 more
doaj +1 more source
Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees. [PDF]
PLoS ONE, 2015 With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone.
Sajid Gul Khawaja +4 more
doaj +1 more source
IEEE Access, 2021 The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs.
Weilong Chen +8 more
doaj +1 more source
Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC
IEEE Access, 2020 Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks.
M. Vinodhini, N. S. Murty, T. K. Ramesh
doaj +1 more source
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC
Journal of Low Power Electronics and Applications, 2019 Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power.
Harikrishna Parmar, Usha Mehta
doaj +1 more source
Implementation of NoC on FPGA with Area and Power Optimization [PDF]
EAI Endorsed Transactions on Context-aware Systems and Applications, 2019 On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size,
Momil Ijaz, Huma Urooj, Muhammad Sethi
doaj +1 more source
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
IEEE Access, 2020 Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is
Waqar Amin +6 more
doaj +1 more source
Journal of Algorithms & Computational Technology, 2016 Three-dimensional network on chip (3D NoC) is developed based on three-dimensional integrated circuit, system on chip and two-dimensional network on chip.
Cui Huang, Dakun Zhang, Guozhi Song
doaj +1 more source