Congestion aware low power on chip protocols with network on chip with cloud security
Journal of Cloud Computing: Advances, Systems and Applications, 2022 This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors.
Suresh Ponnan +4 more
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Automatika, 2023 Systems-on-chips need numerous predesigned cores to advance. NoC enables Multi-Core SoCs (MC_SoCs). Conventional NoC cores use power and latency on multi-hop wired connections.
Dinesh Kumar T.R., Karthikeyan A.
doaj +1 more source
Enhanced overloaded code division multiple access for network on chip
IET Computers & Digital Techniques, 2022 The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On
Behnam Vakili, Morteza Gholipour
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Application Mapping Using Cuckoo Search Optimization With Lévy Flight for NoC-Based System
IEEE Access, 2021 Network on chip (NoC) is a promising communication infrastructure for multiple cores on a chip to exchange data efficiently. In such NoC architecture, application mapping is a process of assigning tasks to the processing cores.
Muhammad Junaid Mohiz +5 more
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Energy Model of Networks-on-Chip and a Bus [PDF]
, 2005 A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching.
Becker, Jens E. +4 more
core +6 more sources
A global wire planning scheme for Network-on-Chip. [PDF]
, 2003 As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a packet switched Network-on-Chip (NoC) architecture was ...
Liu, J. +3 more
core +1 more source
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip [PDF]
, 2008 A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces.
Bekooij, Marco +4 more
core +4 more sources
Designing area optimized application-specific network-on-chip architectures while providing hard QoS guarantees. [PDF]
PLoS ONE, 2015 With the increase of transistors' density, popularity of System on Chip (SoC) has increased exponentially. As a communication module for SoC, Network on Chip (NoC) framework has been adapted as its backbone.
Sajid Gul Khawaja +4 more
doaj +1 more source
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects [PDF]
, 2013 A 64-bit, 8 × 8 mesh network-on-chip (NoC) is presented that uses both new architectural and circuit design techniques to improve on-chip network energy-efficiency, latency, and throughput. First, we propose token flow control, which enables bypassing of
Chiang, Patrick +4 more
core +1 more source
Energy-Efficient NoC for Best-Effort Communication [PDF]
, 2005 A Network-on-Chip (NoC) is an energy-efficient on-chip communication architecture forMulti-Processor System-on-Chip (MPSoC) architectures. In an earlier paper we proposed a energy-efficient reconfigurable circuit-switched NoC to reduce the energy ...
Becker, Jens E. +2 more
core +3 more sources