Results 1 to 10 of about 190,914 (258)
Metasurface-Programmable Wireless Network-On-Chip. [PDF]
Adv Sci (Weinh), 2022 This paper introduces the concept of smart radio environments, currently intensely studied for wireless communication in metasurface‐programmable meter‐scaled environments (e.g., inside rooms), on the chip scale.
F Imani M, Abadal S, Del Hougne P.
europepmc +3 more sources
, 2014 Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and ...
Kundu, Santanu, Chattopadhyay, Santanu
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IET Computers & Digital Techniques, 2009 This special issue on networks-on-chip serves the purpose of collecting timely and selected research contributions on the new frontier of NoC design. The specific focus will be on the architecture layer, while trying to capture how the awareness of the upper and lower design layers affects NoC architecture design.
BERTOZZI, Davide, Kees Goossens
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A Survey of Network-on-Chip Security Attacks and Countermeasures
ACM Computing Surveys, 2021 With the advances of chip manufacturing technologies, computer architects have been able to integrate an increasing number of processors and other heterogeneous components on the same chip.
Subodha Charles, P. Mishra
semanticscholar +1 more source
Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction
Network-on-Chip [Working Title], 2021 Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has
I. Alimi +7 more
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Polymorphic On-Chip Networks [PDF]
2008 International Symposium on Computer Architecture, 2008 As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range
Martha Mercaldi Kim +3 more
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Journal of Lightwave Technology, 2019 Following a decade of radical advances in the areas of integrated photonics and computing architectures, we discuss the use of optics in the current computing landscape attempting to redefine and refine their role based on the progress in both research ...
T. Alexoudi +11 more
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On the capacity of bufferless Networks-on-Chip [PDF]
2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton), 2012 Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs.
Alexander Shpiner +4 more
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Network-on-Chip virtualization in Chip-Multiprocessor Systems
Journal of Systems Architecture, 2012 [EN] It is expected that Chip Multiprocessor Systems (CMPs) will contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. In order to obtain a good CMP utilization several applications will need to coexist in the system and in those cases virtualization of the CMP system will become ...
Francisco Triviño +3 more
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RecoNoC: A reconfigurable network-on-chip [PDF]
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011 This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs.
Robbe Vancayseele +4 more
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