Results 21 to 30 of about 124,522 (260)
Enhanced overloaded code division multiple access for network on chip
IET Computers & Digital Techniques, 2022 The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On
Behnam Vakili, Morteza Gholipour
doaj +1 more source
Wireless Network-on-Chip Security Review: Attack Taxonomy, Implications, and Countermeasures
IEEE Access, 2023 Network-on-chip (NoC) is a critical on-chip communication framework that underpins high-performance multicore computing and network system architectures.
Lashmi Kondoth +3 more
doaj +1 more source
Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
Моделирование и анализ информационных систем, 2017 In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj +1 more source
Synthesis of networks on chips for 3D systems on chips [PDF]
2009 Asia and South Pacific Design Automation Conference, 2009 Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (NoCs) are necessary to efficiently handle the 3D interconnect complexity.
Srinivasan Murali +3 more
openaire +2 more sources
Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications
Journal of Low Power Electronics and Applications, 2017 To allow fast communication—at several Gb/s—of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC).
Fernando Gutierrez
doaj +1 more source
An Optimized Nature-Inspired Metaheuristic Algorithm for Application Mapping in 2D-NoC
Sensors, 2021 Mapping application task graphs on intellectual property (IP) cores into network-on-chip (NoC) is a non-deterministic polynomial-time hard problem. The evolution of network performance mainly depends on an effective and efficient mapping technique and ...
Saleha Sikandar +5 more
doaj +1 more source
Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach
Micromachines, 2023 Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery.
Zhenmin Li +6 more
doaj +1 more source
On the capacity of bufferless Networks-on-Chip [PDF]
2012 50th Annual Allerton Conference on Communication, Control, and Computing (Allerton), 2012 Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In particular, bufferless NoCs require significantly less area and power consumption, but also pose novel major scheduling problems to achieve full capacity. In this paper, we provide first insights on the capacity of bufferless NoCs.
Alexander Shpiner +4 more
openaire +1 more source
RecoNoC: A reconfigurable network-on-chip [PDF]
6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2011 This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs.
Robbe Vancayseele +4 more
openaire +2 more sources
Implementation of NoC on FPGA with Area and Power Optimization [PDF]
EAI Endorsed Transactions on Context-aware Systems and Applications, 2019 On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size,
Momil Ijaz, Huma Urooj, Muhammad Sethi
doaj +1 more source