Results 11 to 20 of about 124,522 (260)
A Scalable Software Defined Network Orchestrator for Photonic Network on Chips
IEEE Access, 2021 Photonic networks and software-defined networks are two promising technologies to improve network-on-chips performance, scalability, and resource utilization.
Doaa A. Hamdi +3 more
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Polymorphic On-Chip Networks [PDF]
2008 International Symposium on Computer Architecture, 2008 As the number of cores per die increases, be they processors, memory blocks, or custom accelerators, the on-chip interconnect the cores use to communicate gains importance. We begin this study with an area-performance analysis of the interconnect design space. We find that there is no single network design that yields optimal performance across a range
Martha Mercaldi Kim +3 more
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Technologies, 2020 Core mapping, in which a core graph is mapped to a network graph to minimize communication, is a common design problem for Systems-on-Chip interconnected by a Network-on-Chip. In conventional multiprocessors, this mapping is area-agnostic as the cores in
Jan Moritz Joseph +4 more
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Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
IEEE Access, 2020 Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is
Waqar Amin +6 more
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Congestion aware low power on chip protocols with network on chip with cloud security
Journal of Cloud Computing: Advances, Systems and Applications, 2022 This article is to analyze the bottleneck problems of NoC in many more applications like multi-processor communication, computer architectures, and network interface processors.
Suresh Ponnan +4 more
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A Routing-Aware Simulated Annealing-based Placement Method in Wireless Network on Chips [PDF]
Journal of Artificial Intelligence and Data Mining, 2020 Wireless network on chip (WiNoC) is one of the promising on-chip interconnection networks for on-chip system architectures. In addition to wired links, these architectures also use wireless links.
A.R. Tajary, E. Tahanian
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Congestion-aware wireless network-on-chip for high-speed communication
Automatika, 2020 The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC ...
M. Devanathan +2 more
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Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems
IEEE Access, 2021 Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems.
Bichi Bashir Yusuf +3 more
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A Novel 3D Mesh-Based NoC Architecture for Performance Improvement
Majlesi Journal of Electrical Engineering, 2022 Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is also known as a basic NoC architecture characterized by better energy consumption
Navid Habibi +2 more
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Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC
IEEE Access, 2020 Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks.
M. Vinodhini, N. S. Murty, T. K. Ramesh
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