Results 21 to 30 of about 11,636 (194)
Design and implementation of the Quarc network on-chip [PDF]
, 2009 Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip.
Maji, P.P. +2 more
core +1 more source
IEEE Access, 2021 The academia and industry have been pursuing network-on-chip (NoC) related research since two decades ago when there was an urgency to respond to the scaling and technological challenges imposed on intra-chip communication in SoC designs.
Weilong Chen +8 more
doaj +1 more source
Cycle-accurate evaluation of reconfigurable photonic networks-on-chip [PDF]
, 2010 There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores.
Artundo, Iñigo +4 more
core +1 more source
Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC
IEEE Access, 2020 Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks.
M. Vinodhini, N. S. Murty, T. K. Ramesh
doaj +1 more source
Design and implementation 4x4 Network on Chip (NoC) using FPGA
Periodicals of Engineering and Natural Sciences (PEN), 2022 Network on Chip is one of the most crucial in the development of the networks and routers in new days due to the improvement that make through way of sending huge packets of data and technology and protocol that used for sending the packets between IP cores.
Waleed K. Al-Azzwai +2 more
openaire +1 more source
RecoNoC: a reconfigurable network-on-chip [PDF]
, 2011 This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts.
Al Farisi, Brahim +4 more
core +2 more sources
ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC
Journal of Low Power Electronics and Applications, 2019 Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power.
Harikrishna Parmar, Usha Mehta
doaj +1 more source
Implementation of NoC on FPGA with Area and Power Optimization [PDF]
EAI Endorsed Transactions on Context-aware Systems and Applications, 2019 On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size,
Momil Ijaz, Huma Urooj, Muhammad Sethi
doaj +1 more source
Fast, Accurate and Detailed NoC Simulations [PDF]
, 2007 Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer's requirements. Fast exploration of this parameter space is only possible at a high-level and several methods have been proposed.
Hölzenspies, P.K.F. +2 more
core +2 more sources
NoCo: ILP-based worst-case contention estimation for mesh real-time manycores [PDF]
, 2019 Manycores are capable of providing the computational demands required by functionally-advanced critical applications in domains such as automotive and avionics.
Abella Ferrer, Jaume +4 more
core +1 more source