Results 21 to 30 of about 1,145 (180)
Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs
Network-on-chip (NoC) is evolving as a better substitute for incorporating a large number of cores on a single system-on-chip (SoC). The dependency on multi-core systems to accomplish the high-performance constraints of composite embedded applications is
Waqar Amin +6 more
doaj +1 more source
Three-dimensional network on chip (3D NoC) is developed based on three-dimensional integrated circuit, system on chip and two-dimensional network on chip.
Cui Huang, Dakun Zhang, Guozhi Song
doaj +1 more source
According to the International Technology Roadmap for Semiconductors, improving characteristics of metal wires will no longer satisfy performance requirements, and new interconnect paradigms are needed.
Chunhua Xiao, Weichen Liu
doaj +1 more source
A New Efficient and Reliable Dynamically Reconfigurable Network-on-Chip
We present a new reliable Network-on-Chip (NoC) suitable for Dynamically Reconfigurable Multiprocessors on Chip systems. The proposed NoC is based on routers performing online error detection of routing algorithm and data packet errors.
Cédric Killian +3 more
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Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability.
Samala Jagadheesh +3 more
doaj +1 more source
The trend of unsustainable power consumption and large memory bandwidth demands in massively parallel multicore systems, with the advent of the big data era, has brought upon the onset of alternate computation paradigms utilizing heterogeneity, specialization, processor-in-memory and approximation.
Rahul Boyapati +4 more
openaire +3 more sources
Applying Partial Power-Gating to Direction-Sliced Network-on-Chip
Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating
Feng Wang, Xiantuo Tang, Zuocheng Xing
doaj +1 more source
Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge.
Alireza Monemi +2 more
doaj +1 more source
Congestion-aware wireless network-on-chip for high-speed communication
The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC ...
M. Devanathan +2 more
doaj +1 more source
Spatial Cell Death and Oxidative Stress Dynamics in Gas Plasma‐Treated Tumor Tissues
Schematic representation of the four experimental models to study tissue penetration and oxidation. Four tissue models were used. Human pancreatic cancer cells were grown on the chorioallantois membrane of chicken embryos and gas plasma‐treated in ovo, murine colorectal tumor tissue was gas plasma‐exposed ex vivo, murine squamous cell carcinoma cells ...
Anke Schmidt +4 more
wiley +1 more source

