Results 31 to 40 of about 132,420 (284)
Hotspots Reduction for GALS NoC Using a Low-Latency Multistage Packet Reordering Approach
Micromachines, 2023 Traffic splitting enabled by Globally Asynchronous Locally Synchronous (GALS) Network-on-chip (NoC) brings multipath routing capability, which significantly increases link bandwidth at the cost of out-of-order packet delivery.
Zhenmin Li +6 more
doaj +1 more source
Energy Model of Networks-on-Chip and a Bus [PDF]
, 2005 A Network-on-Chip (NoC) is an energy-efficient onchip communication architecture for Multi-Processor Systemon-Chip (MPSoC) architectures. In earlier papers we proposed two Network-on-Chip architectures based on packet-switching and circuit-switching.
Becker, Jens E. +4 more
core +6 more sources
Design and implementation of the Quarc network on-chip [PDF]
, 2009 Networks-on-Chip (NoC) have emerged as alternative to buses to provide a packet-switched communication medium for modular development of large Systems-on-Chip.
Maji, P.P. +2 more
core +1 more source
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip [PDF]
, 2008 A Network on Chip (NoC) with end-to-end flow control is modelled by a cyclo-static dataflow graph. Using the proposed model together with state-of-the-art dataflow analysis algorithms, we size the buffers in the network interfaces.
Bekooij, Marco +4 more
core +4 more sources
Anticipative QoS Control: A Self-Reconfigurable On-Chip Communication
Micromachines, 2022 A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting ...
Wen-Chung Tsai +3 more
doaj +1 more source
An Energy and Performance Exploration of Network-on-Chip Architectures [PDF]
, 2009 In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they ...
Arnab Banerjee +6 more
core +3 more sources
Implementation of NoC on FPGA with Area and Power Optimization [PDF]
EAI Endorsed Transactions on Context-aware Systems and Applications, 2019 On-chip bus-based communication has many shortcomings to it, including resource sharing, delay, latency and cost (power and area). Network on Chip (NoC) is an innovation that is planned to eliminate the shortcomings to buses such as compact systems,size,
Momil Ijaz, Huma Urooj, Muhammad Sethi
doaj +1 more source
A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems
IET Computers & Digital Techniques, 2023 In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered.
Saleh Abdelhafeez, Shadi M. S. Harb
doaj +1 more source
Application-Specific Heterogeneous Network-on-Chip Design [PDF]
, 2013 Cataloged from PDF version of article.As a result of increasing communication demands, application-specific and scalable Network-on-Chips (NoCs) have emerged to connect processing cores and subsystems in Multiprocessor System-on-Chips.
Akturk, I. +3 more
core +1 more source
A Time-Predictable Memory Network-on-Chip [PDF]
, 2014 To derive safe bounds on worst-case execution times (WCETs), all components of a computer system need to be time-predictable: the processor pipeline, the caches, the memory controller, and memory arbitration on a multicore processor.
Chong, David Vh +2 more
core +1 more source