Results 91 to 100 of about 7,265 (245)
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez +10 more
wiley +1 more source
Gaussian Multiple Access Channels with One-Bit Quantizer at the Receiver †,‡
The capacity region of a two-transmitter Gaussian multiple access channel (MAC) under average input power constraints is studied, when the receiver employs a zero-threshold one-bit analogue-to-digital converter (ADC).
Borzoo Rassouli +2 more
doaj +1 more source
Channel AoA estimation for massive MIMO systems using one-bit ADCs
Although massive multiple-input multiple-output (MIMO) can enhance the overall system performance significantly, it could suffer from high cost and power consumption issues due to using a large number of radio frequency (RF) chains. Two different approaches are commonly exploited to overcome these issues. The first approach is using hybrid beamforming,
Hwanjin Kim, Junil Choi
openaire +2 more sources
On the Role of Preprocessing and Memristor Dynamics in Reservoir Computing for Image Classification
ABSTRACT Reservoir computing (RC) is an emerging recurrent neural network architecture that has attracted growing attention for its low training cost and modest hardware requirements. Memristor‐based circuits are particularly promising for RC, as their intrinsic dynamics can reduce network size and parameter overhead in tasks such as time‐series ...
Rishona Daniels +4 more
wiley +1 more source
End-to-End Quantization Co-Design for MHz GaN Converters using Dither and Sigma-Delta Modulation
We study end-to-end quantization in digitally controlled MHz-range GaN DC–DC converters, spanning the analog-to-digital converter (ADC), fixed-point controller, and digital pulse-width modulator (DPWM).
Nuha Adnan Al-Obaidi, Ali Nawar
doaj +1 more source
Passive resistive memory arrays promise efficient in‐memory computing but suffer from sneak paths and programming variability. Here, highly uniform 32 × 32 passive RRAM crossbars are programmed with multilevel precision below 3% error and 99.5% yield.
S. Ricci +6 more
wiley +1 more source
Blind Estimation of Sparse Broadband Massive MIMO Channels With Ideal and One-bit ADCs
Submitted to IEEE Transactions on Signal ...
Amine Mezghani, A. Lee Swindlehurst
openaire +4 more sources
Capacitive, charge‐domain compute‐in‐memory (CIM) stores weights as capacitance,eliminating DC sneak paths and IR‐drop, yielding near‐zero standbypower. In this perspective, we present a device to systems level performance analysis of most promising architectures and predict apathway for upscaling capacitive CIM for sustainable edge computing ...
Kapil Bhardwaj +2 more
wiley +1 more source
A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices
Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life.
Dina M. Ellaithy
doaj +1 more source
A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song +21 more
wiley +1 more source

