Results 31 to 40 of about 32,736 (268)

All‐in‐One Analog AI Hardware: On‐Chip Training and Inference with Conductive‐Metal‐Oxide/HfOx ReRAM Devices

Advanced Functional Materials, EarlyView.
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Tommaso Stecconi, Folkert Horst, Laura Bégon‐Lours, Matteo Galetta, Antonio La Porta, Nikhil Garg, Fabien Alibart, Bert Jan Offrein, Valeria Bragaglia   +11 more
wiley   +1 more source

Guarding the Gates: Exploring a Theological–Philosophical Framework for Cybersecurity and Spiritual Discernment in the Digital Age

Businesses
This paper examines the intersection between Christian theological principles and contemporary cybersecurity challenges, with a focus on the specific vulnerabilities and responsibilities of faith-based organizations.
Laura A. Jones
doaj   +1 more source

A method for real-time memory efficient implementation of blob detection in large images [PDF]

Serbian Journal of Electrical Engineering, 2017
In this paper we propose a method for real-time blob detection in large images with low memory cost. The method is suitable for implementation on the specialized parallel hardware such as multi-core platforms, FPGA and ASIC.
Petrović Vladimir L., Popović-Božović Jelena S.   +1 more
doaj   +1 more source

Monolithic Oxidation Enables Ultrathin Vertically Graded Tantalum Oxide for Low‐Voltage, Low‐Variability Memristive Switching

Advanced Functional Materials, EarlyView.
Monolithic UV‐ozone oxidation of Ta forms an ultrathin Ta2O5/TaOx bilayer enabling resistive switching with a vertical defect gradient. A stoichiometric surface layer over an oxygen‐deficient sublayer promotes localized filament nucleation near the top interface, enabling low‐voltage operation, and reduced cycle‐to‐cycle variability.
Seunghoon Yang, Dong Hyun Lee, Conan Weiland, Won‐Il Lee, Kim Kisslinger, Mingzhao Liu, Aswin kumar Anbalagan, Xiao Tong, Soumyajit Mandal, Nikhil Tiwale, Houk Jang, Chang‐Yong Nam   +11 more
wiley   +1 more source

Research on parallelization clustering algorithm for power communication big data

Dianzi Jishu Yingyong, 2018
With the development of power communication technology, a large number of distributed power communication subsystems and massive power communication data have been generated.
Zeng Ying, Li Xingnan, Liu Xinzhan
doaj   +1 more source

EVMTracer: Dynamic Analysis of the Parallelization and Redundancy Potential in the Ethereum Virtual Machine

IEEE Access, 2023
Ethereum is one of the first blockchains executing smart contracts, i.e., financial applications directly executed on the ledger using a virtual machine.
Xiaowen Hu, Bernd Burgstaller, Bernhard Scholz   +2 more
doaj   +1 more source

Emerging Post‐CMOS Hardware Neurons for Brain‐Inspired Computing: Devices, Circuits, and System Integration

Advanced Functional Materials, EarlyView.
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan, Hocheon Yoo, Benoît H. Lessard, Ioannis Kymissis, Chang‐Hyun Kim   +4 more
wiley   +1 more source

A Scheduling Method of Moldable Parallel Tasks Considering Speedup and System Load on the Cloud

IEEE Access, 2019
The moldable parallel task (MPT) is a kind of parallel task that their sub-tasks hold the resources exclusively, which has been widely used in different areas. Our paper focuses on the scheduling of moldable tasks when every sub-task supports time-slice.
Jianmin Li, Ying Zhong, Xin Zhang
doaj   +1 more source

Neuromorphic Electronics for Intelligence Everywhere: Emerging Devices, Flexible Platforms, and Scalable System Architectures

Advanced Materials, EarlyView.
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj, Roshni Satheesh Babu, Yuxin Xia, Eva Bestelink, Radu Sporea, Nikos Hastas, Ioannis Zeimpekis, Dimitra G. Georgiadou, Sayani Majumdar   +8 more
wiley   +1 more source

Hardware acceleration of number theoretic transform for zk‐SNARK

Engineering Reports, EarlyView., 2023
An FPGA‐based hardware accelerator with a multi‐level pipeline is designed to support the large‐bitwidth and large‐scale NTT tasks in zk‐SNARK. It can be flexibly scaled to different scales of FPGAs and has been equipped in the heterogeneous acceleration system with the help of HLS and OpenCL.
Haixu Zhao, Dong Ding, Feng Wang, Pengcheng Hua, Ning Wang, Qin Wu, Zhilei Chai   +6 more
wiley   +1 more source