Results 261 to 270 of about 46,362 (283)

Parasitic Capacitances and Their Linear Approximation

1990
In Chapters 4, 5 and 6, an efficient numerical technique for computing the parasitic capacitances in VLSI circuits has been presented. Although the numerical techniques are powerful, they still require a great amount of computer resources for complicated geometries. It is expensive to handle a large layout with them.
Patrick Dewilde, Zhen-Qui Ning
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Benchmarks for interconnect parasitic resistance and capacitance

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2004
Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors ...
N.S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, C. Cantrell   +7 more
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Minimization of parasitic capacitances in VMOS transistors

1976 International Electron Devices Meeting, 1976
Process techniques for the reduction of parasitic capacitances in VMOS transistors (1) have been developed. Significant reductions in gate to drain overlap capacitance and side wall component of the junction capacitance have been achieved for a high performance VMOS process.
I.S. Bhatti, T.J. Rodgers, J.R. Edwards
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Parasitic capacitances of Dual-K spacer FinFET

2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 2016
This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed.
Shilpa Bisnoi, Sudeb Dasgupta
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Investigating parasitic capacitance cancellation for EMI suppression

2009 IEEE Vehicle Power and Propulsion Conference, 2009
This paper begins with the review of different parasitic capacitance cancellation techniques. The effectiveness of different cancellation techniques is discussed. The critical parameters and constraints for each cancellation technique are identified. The cancellation techniques are then applied to different applications based on their characteristics ...
null Shuo Wang, F.C. Lee
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Parasitic influences in a capacitive transducer behavior

Proceedings of the 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011
The most common parasitic effects involved in a capacitive measurement process are the fringing phenomenon, the error due to unparallel armatures, the capillarity phenomenon, the temperature and humidity influence and the electrical parasitic capacitances induced by the PCB connection traces.
Vlad Bande, Ioan Ciascai, Dan Pitica
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Stability of a circuit with parasitic capacitances

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002
A novel algorithm which is based on the linear programming technique is proposed to test the stability property of a circuit. This algorithm is efficient and non-Lyapunov equation based. Parasitic capacitances which may de-stabilize a circuit can be located.
S.W. Ng, Y.S. Lee, C.K. Tse, S.C. Wong
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Measurements and extractions of parasitic capacitances in ulsi layouts

IEEE Transactions on Electron Devices, 2003
This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications.
BRAMBILLA, ANGELO MAURIZIO, MAFFEZZONI, PAOLO, L. Bortesi, L. Vendrame   +3 more
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A simple analog interface for capacitive sensor with offset and parasitic capacitance

2015 Annual IEEE India Conference (INDICON), 2015
In this paper, a simple but efficient analog interface circuit for floating capacitive sensor is presented. In most of the capacitive sensor, the offset and parasitic components are associated with the sensor and varies with the measurand. In these sensors, the change in the sensor capacitance due to measurand can be very small but having a relatively ...
Shahid Malik, Tarikul Islam, Kaushal Kishore, Krishan Kumar, S.A. Akbar, B.A. Botre   +5 more
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Parasitic capacitance removal of sub-100nm p-MOSFETs using capacitance–voltage measurements

Solid-State Electronics, 2012
Abstract Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results.
Daniel R. Steinke, Joseph Piccirillo, Steven C. Gausepohl, Saikumar Vivekand, Martin P. Rodgers, Ji Ung Lee   +5 more
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