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Introduction of parasitic capacitance and methods of reducing its capacitance

Applied and Computational Engineering
This paper aims to introduce some basic knowledge of parasitic capacitors and how to reduce the impact of parasitic capacitors in theory and in practice. In the production and processing and daily life, people will be more or less to the use of capacitors.
Changqing Bao, Hongjia Zhu, Jiayu Liu
openaire   +1 more source

Parasitic capacitance effects of planar resistors

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989
The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
openaire   +1 more source

Efficient extraction of metal parasitic capacitances

Proceedings International Conference on Microelectronic Test Structures, 2002
Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
openaire   +1 more source

Parasitic Capacitances in Double Gate MOSFET

2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward.
Viranjay M. Srivastava   +3 more
openaire   +1 more source

FCAP2: Parasitic Capacitance/Resistance Simulator

1986
To simulate the parasitic capacitance/resistance, it is necessary to solve the Poisson (or Laplace) equation in at least two dimensions with arbitrary input geometry.
Kit Man Cham   +3 more
openaire   +1 more source

Parasitic Capacitance Modeling of Copper-Foiled Medium-Voltage Filter Inductors Considering Fringe Electrical Field

IEEE Transactions on Power Electronics, 2021
Stig Munk-Nielsen   +2 more
exaly  

Parasitic Capacitance-Free Flexible Tactile Sensor with a Real-Contact Trigger

Soft Robotics, 2022
Hyungpil Moon, Hyuneui Lim, Sunjong Oh
exaly  

Physics-Based Modeling of Parasitic Capacitance in Medium-Voltage Filter Inductors

IEEE Transactions on Power Electronics, 2021
Stig Munk-Nielsen   +2 more
exaly  

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