Results 261 to 270 of about 10,280 (293)
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Parasitic influences in a capacitive transducer behavior
Proceedings of the 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011The most common parasitic effects involved in a capacitive measurement process are the fringing phenomenon, the error due to unparallel armatures, the capillarity phenomenon, the temperature and humidity influence and the electrical parasitic capacitances induced by the PCB connection traces.
Vlad Bande, Ioan Ciascai, Dan Pitica
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Impact of parasitic capacitances on the performance of SAR ADCs based on capacitive arrays
2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2010This paper analyzes the effect of parasitic capacitances on the performance of SAR ADCs based on capacitive arrays, usually employed in biomedical sensors due to their low-power consumption. The paper compares the most common architectures employed for capacitive DACs, analyzing the different effects that parasitic capacitances have on their linearity ...
Alberto Rodriguez-Perez +3 more
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IEEE Electron Device Letters, 2017
In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently.
Sourabh Khandelwal +4 more
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In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently.
Sourabh Khandelwal +4 more
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Minimize the delay of parasitic capacitance and modeling in RLC circuit
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009This paper shows that how to minimize the delay. We changed several elements to minimize the delay in the circuit. Simulation results show the best effect when the value of parasitic capacitance is changed. We found eligible point by simulating Parasitic Capacitance case by case based and proved it. Types of case are Elmore delay, Interconnection delay,
Dukgwon Lee +6 more
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Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference, 2004Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow.
Anuradha Agarwal +3 more
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Compensation of Parasitic Capacitances in Broadband Filters
IEEE Transactions on Circuit Theory, 1967Methods are presented to anticipate the effect of the coils parasitic capacitances in the implementation of broadband filters. The case of uniform parasitic capacitances leads to a process in some respect analogous to the classical predistortion theory for losses: the compensation problem can be solved by operating solely on the transmittance function.
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Parasitic Capacitance-Free Flexible Tactile Sensor with a Real-Contact Trigger
Soft Robotics, 2022Youngdo Jung +2 more
exaly
Accurate estimation of parasitic capacitances in analog circuits
Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004Anuradha Agarwal +3 more
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Calculation and modelling of transformer parasitic capacitance
IET Conference Proceedings, 2022W. Guo, J. Yang, R. Li
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