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Colossal emergent inductance in a molecular memristor. [PDF]
Sci RepOshima Y +4 more
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Capacitive in-memory vector-matrix multiplication computing with charge-trap memcapacitors. [PDF]
Nano ConvergYu J, Hwang H, Kim H, Choi WY.
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Research on temperature characteristic of parasitic capacitance in MEMS capacitive accelerometer
Sensors and Actuators A: Physical, 2019Abstract In MEMS capacitive accelerometer, parasitic capacitance is a serious problem, and its change over temperature would deteriorate performance of MEMS accelerometer. Yet, the temperature characteristic of parasitic capacitance hasn’t got enough research. In this work, the parasitic capacitance and its effect on bias drift are quantificationally
Xianshan Dong, Junhua Zhu
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Parasitic capacitance of submicrometer MOSFET's
IEEE Transactions on Electron Devices, 1999We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer ...
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Rethinking Basic Assumptions for Modeling Parasitic Capacitance in Inductors [PDF]
IEEE Transactions on Power Electronics, 2022 This article rethinks the basic assumptions often used in analytically modeling parasitic capacitance in inductors. These assumptions are classified in two commonly-used physics-based analysis methods: the lumped capacitor network method and the energy ...
Zhan Shen +2 more
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Stability of a circuit with parasitic capacitances
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002A novel algorithm which is based on the linear programming technique is proposed to test the stability property of a circuit. This algorithm is efficient and non-Lyapunov equation based. Parasitic capacitances which may de-stabilize a circuit can be located.
Shek-Wai Ng +3 more
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Benchmarks for interconnect parasitic resistance and capacitance
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2004Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors ...
N. S. Nagaraj +7 more
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Parasitic capacitance modeling for multilevel interconnects
Asia-Pacific Conference on Circuits and Systems, 2003The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be ...
Sadahiro Tani +8 more
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Reducing the Effect of Parasitic Capacitance on the Micro-capacitive Humidity Sensor
2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2019It is the most important issue of how the effects of parasitic capacitance can be reduced during the development of micro-capacitive humidity sensor systems. For this purposes, in this paper, step-by-step optimizations were carried out through packaging and circuit to achieve a high-precision, high-stability, and high-repetition humidity sensor system.
Jihang Liu +5 more
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