Results 251 to 260 of about 144,693 (302)
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ICASSP '78. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005
This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. Reddy, E. Fountain
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This paper deals with the design, construction and evaluation of a Digital Phase-Locked Loop. An exclusive OR gate serves as a linear phase detector. The integrator consists of a cascade of up/down decade counters. The D.C. value of each cycle from the phase detector is measured and accumulated. The rate of integration is determined by the clock input.
C. Reddy, E. Fountain
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2015
One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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One of the most challenging tasks in analog circuit design is to adapt a functional block to ever-new CMOS process technologies. For digital circuits, the number of gates per square milimeter approximately doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated ...
Basab Bijoy Purkayastha +1 more
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IETE Journal of Education, 2011
AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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AbstractThe paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed.
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IEE Colloquium on Phase Lock Loops: Theory and Practice, 1999
This paper discusses the design and implementation of a current-mode phase-locked loop (PLL) using translinear and log-domain circuits. The paper illustrates the use of 'log-domain state space' design equations for both the synthesis and analysis of the log-domain sub-circuits within the complete PLL architecture.
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This paper discusses the design and implementation of a current-mode phase-locked loop (PLL) using translinear and log-domain circuits. The paper illustrates the use of 'log-domain state space' design equations for both the synthesis and analysis of the log-domain sub-circuits within the complete PLL architecture.
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2022
This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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This thesis was scanned from the print manuscript for digital preservation and is copyright the author. Researchers can access this thesis by asking their local university, institution or public library to make a request on their behalf. Monash staff and postgraduate students can use the link in the References field.
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Genome folding through loop extrusion by SMC complexes
Nature Reviews Molecular Cell Biology, 2021Iain F Davidson, Jan-Michael Peters
exaly
Phosphorus recovery and recycling – closing the loop
Chemical Society Reviews, 2021Andrew R Jupp +2 more
exaly
Closed-loop neuromodulation in an individual with treatment-resistant depression
Nature Medicine, 2021Katherine W Scangos +2 more
exaly
2003
A phase-locked loop circuit has an output amplifier (27) and a main feedback path from the output of the output amplifier (27). A subsidiary feedback path is provided directly from the output of the circuit's VCO (32). At the start of operation, the output amplifier (27) is disabled and the subsidiary feedback path is used until lock is achieved.
NOKIA CORP, MIDTGAARD JACOB, BAGGER OLUF
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A phase-locked loop circuit has an output amplifier (27) and a main feedback path from the output of the output amplifier (27). A subsidiary feedback path is provided directly from the output of the circuit's VCO (32). At the start of operation, the output amplifier (27) is disabled and the subsidiary feedback path is used until lock is achieved.
NOKIA CORP, MIDTGAARD JACOB, BAGGER OLUF
openaire +1 more source