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DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGY

SSRN Electronic Journal
Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design.
openaire   +2 more sources

A Phase Lock Loop (PLL) System for Frequency Variation Tracking during General Anesthesia

2014
We present a novel technique derived from the communication systems area, able to track frequency changes in electroencephalogram (EEGs) signals collected from patients subjected to general anesthesia. The technique is based on a phase lock loop (PLL) circuit, which is used for example for radio-FM demodulation.
C. A. Teixeira   +4 more
openaire   +1 more source

MALHA DE SINCRONISMO DE FASE - PLL (PHASE-LOCKED LOOP)

2023
André Alves Ferreira   +3 more
openaire   +1 more source

Constant Vibration Amplitude Method of Piezoelectric Transducer Using A PLL (Phase Locked Loop)

Japanese Journal of Applied Physics, 1985
In an ultrasonic cleaning machine a problem form the standpoint of cleaning efficiency is to secure constant vibration amplitude of the transducer even when fluctuations of the load arise. This report deals with a method of obtaining constant vibration amplitude by using a PLL for the transducer and a π-type impedance inverting circuit for the ...
openaire   +1 more source

An Improved Linear Phase-Locked Loop (PLL) with notch Pre-filter

2021 IEEE 2nd China International Youth Conference on Electrical Engineering (CIYCEE), 2021
Xiaolong He, Yun Xu
openaire   +1 more source

Genome folding through loop extrusion by SMC complexes

Nature Reviews Molecular Cell Biology, 2021
Iain F Davidson, Jan-Michael Peters
exaly  

Sampling phase lock loop (PLL) with low power clock buffer

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions ...
Gao, X.   +6 more
openaire  

Phosphorus recovery and recycling – closing the loop

Chemical Society Reviews, 2021
Andrew R Jupp   +2 more
exaly  

Closed-loop neuromodulation in an individual with treatment-resistant depression

Nature Medicine, 2021
Katherine W Scangos   +2 more
exaly  

Loop extrusion as a mechanism for formation of DNA damage repair foci

Nature, 2021
Coline Arnould   +2 more
exaly  

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