Results 171 to 180 of about 2,094 (182)

Phase-Locked Loop (PLL) Techniques for Grid Synchronization: A Comprehensive Review

2024 Second International Conference on Emerging Trends in Information Technology and Engineering (ICETITE)
Balu Priyanka, Sri Karthik V, M.C. Lavanya, Malola Krishnan V   +3 more
openaire   +1 more source

Pattern recognition via synchronization in phase-locked loop neural networks

IEEE Transactions on Neural Networks, 2000
Frank C Hoppensteadt, Eugene M Izhikevich   +1 more
exaly  

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

IEEE Journal of Solid-State Circuits, 2014
Ahmed Musa, Wei Deng, Teerachot Siriburanon   +2 more
exaly  

Conventional Synchronous Reference Frame Phase-Locked Loop is an Adaptive Complex Filter

IEEE Transactions on Industrial Electronics, 2015
Saeed Golestan, Josep M Guerrero
exaly  

Five Approaches to Deal With Problem of DC Offset in Phase-Locked Loop Algorithms: Design Considerations and Performance Evaluations

IEEE Transactions on Power Electronics, 2016
Saeed Golestan, Josep M Guerrero, Gevork B Gharehpetian   +2 more
exaly  

MAF-PLL With Phase-Lead Compensator

IEEE Transactions on Industrial Electronics, 2014
Saeed Golestan, Josep M Guerrero, Abdullah Abusorrah   +2 more
exaly  

Reduction of Phase Noise and Lock Time in Low Power Phase Lock Loop (PLL)

Journal of Computational and Theoretical Nanoscience, 2018
Amit Kumar, Shailendra Singh Ojha, Shyam Akashe   +2 more
openaire   +1 more source

Design and Performance Test of Three Phased Synchronous Reference Frame-Phase Locked Loop (SRF-PLL) using DSPIC30F4011

2018
Iwan Setiawan, Susatyo Handoko
exaly  

A 10GHz Low-Jitter Cryogenic Phase-Locked Loop (PLL) For Quantum Applications

A 10GHz Low-Jitter Cryogenic Phase-Locked Loop (PLL) For Quantum Applications
Xiaoran Wang, Davide Braga, Troy England, Kushal Das, Neil Dick, Farah Fahim, Scott Holm, Alireza Moini, Frederic Nolet, Paul Rubinov, Len Sanderson, Yash Saxena   +11 more
openaire   +1 more source

Research on Failure Mechanism of SerDes Phase-Lock-Loop (PLL) Lose Lock

2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
Xixiong Wei, Xinyi Lin, Shuanshe Chao, Yaping Huang, Dan Yang, Na Mei, Jie Hu   +6 more
openaire   +1 more source