Results 161 to 170 of about 4,801,356 (217)

Development of low power Phase-Locked Loop (PLL) and PLL-based serial transceiver

Journal of Instrumentation, 2012
The design and measurement results of a low power Phase-Locked Loop (PLL) and a PLL-based transceiver for applications in readout systems of particle physics detectors, designed and fabricated in a 0.35 ?m CMOS technology, are presented. The measurements show that the prototype PLL is fully functional and generates the clock signal in the frequency ...
J Moroń, M Firlej, M Idzik
openaire   +1 more source

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

IEEE Transactions on Industrial Electronics, 1996
Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters.
Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano   +3 more
openaire   +2 more sources

Analysis of lock-loss events in discrete-time phase locked loop (PLL)

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., 2005
Lock-loss phenomena were studied extensively for continuous-time phase locked loop (PLL), and closed form analytical expressions for the mean time to lose lock (MTLL) has been derived under the assumptions that the input is a phase modulated sine wave, and that the additive noise associated with the input can be added to the detector output.
Liran Brecher, Naftali Sommer, Ehud Weinstein   +2 more
openaire   +2 more sources

Computer simulation and parameter optimization of phase-locked loops (PLL)

SIMULATION, 1971
The automatic control and simulation of phased- locked loops (PLL) is treated with particular em phasis on the use of analog and digital computer simulation techniques. The object is to obtain an adequate mathematical model for the PLL and then to use this model to optimize parameters and investi gate pull-in performance.
openaire   +1 more source

ASIC clock distribution using a phase locked loop (PLL)

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 2002
Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance. >
openaire   +1 more source

On-Line Musical Beat Tracking with Phase-Locked-Loop (PLL) Techniique

2007 Digest of Technical Papers International Conference on Consumer Electronics, 2007
An on-line beat tracking algorithm based on the digital phase-locked-loop (PLL) technique is proposed in this work, which estimates both the music tempo and the position of beat pulses in real time. In addition to a detailed description of the proposed algorithm, we show that the PLL-technique is effective in its tracking performance and simple to ...
Yu Shiu, C.-C. Jay Kuo
openaire   +1 more source

Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures

IEEE Access, 2022
Woorham Bae
exaly  

Phase lock loops (PLLS) and methods of initializing PLLS

2021
MAR WING, ZINGG RETO
openaire   +1 more source

Synchronous Reference Frame Single-Phase Phase-Locked Loop (PLL) Algorithm Based on Half-Cycle DFT

IET Power Electronics, 2020
Yezhao Liu, Guojun Tan, Tao Xia
exaly  

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector

IEEE Journal of Solid-State Circuits, 2022
Suneui Park, Jaehyouk Choi, Yoonseo Cho
exaly