Results 141 to 150 of about 2,094 (182)
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Optimization of Phase-Locked Loop (PLL) System Parameters
2004The paper investigates the optimization of parameters for digital phase-locked loop (PLL) systems in order to enhance noise immunity. A Gaussian distribution is assumed for phase deviations of input sync pulses. A mathematical model of the PLL is developed, and a quality criterion based on the output phase deviation variance is proposed. Constraints on
Abdullayev, Isa M. +1 more
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Computer simulation and parameter optimization of phase-locked loops (PLL)
SIMULATION, 1971The automatic control and simulation of phased- locked loops (PLL) is treated with particular em phasis on the use of analog and digital computer simulation techniques. The object is to obtain an adequate mathematical model for the PLL and then to use this model to optimize parameters and investi gate pull-in performance.
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Trusted verification test bench development for Phase-Locked Loop (PLL) hardware insertion
2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013Trusted design and verification presents new challenges for the case of using Intellectual Property (IP) in mixed signal systems. A Digitally Controlled Oscillator (DCO) subcomponent of a Phase-Locked Loop (PLL) is utilized as an example through which the presented verification principles may be applied to PLL tests on the Texas Instruments Analog ...
Adam G. Kimura +4 more
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1992
Eine Phasenregelschleife (PLL, Phase Locked Loop) ist ein Schaltkreis der einem externen Referenzsignal erlaubt, die Frequenz und die Phase eines Oszillators in der Schleife zu steuern. Die Frequenz des Oszillators in der Schleife kann dabei dieselbe wie die Referenzfrequenz sein oder ein Vielfaches davon.
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Eine Phasenregelschleife (PLL, Phase Locked Loop) ist ein Schaltkreis der einem externen Referenzsignal erlaubt, die Frequenz und die Phase eines Oszillators in der Schleife zu steuern. Die Frequenz des Oszillators in der Schleife kann dabei dieselbe wie die Referenzfrequenz sein oder ein Vielfaches davon.
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2010
PLL is the heart of practically all electronic components and or modules where different clock frequencies are required to synchronize the data transmitting and receiving to and from externals respectively. The input clock to the PLL is much lower than the DSP maximum clock frequency.
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PLL is the heart of practically all electronic components and or modules where different clock frequencies are required to synchronize the data transmitting and receiving to and from externals respectively. The input clock to the PLL is much lower than the DSP maximum clock frequency.
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ASIC clock distribution using a phase locked loop (PLL)
[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 2002Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance. >
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Grid Connected Photovoltaic (PV) Inverter with Robust Phase-Locked Loop (PLL)
2006 IEEE/PES Transmission & Distribution Conference and Exposition: Latin America, 2006An array of solar panels is connected to the mains through a three-phase active voltage-source inverter and a step-up transformer. The inverter synchronizes to the grid by means of a robust phase-locked loop (PLL), using input's quadrate method, and a multi-variable filter removes voltage harmonics caused by unbalance and distortion.
T. Ostrem +3 more
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2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013
This preliminary study reviews important features of the injection locked Synchronous Oscillator (SO), which is a multi-functional network to synchronize, track, and amplify a reference signal. The SO can reduce the phase noise and the acquisition time of the system. The Coherent Phase-Locked Synchronous Oscillator (CPSO) is then presented and analyzed
Feiran Lei, Marvin H. White
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This preliminary study reviews important features of the injection locked Synchronous Oscillator (SO), which is a multi-functional network to synchronize, track, and amplify a reference signal. The SO can reduce the phase noise and the acquisition time of the system. The Coherent Phase-Locked Synchronous Oscillator (CPSO) is then presented and analyzed
Feiran Lei, Marvin H. White
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Comparison of two methods for addressing DC component in phase-locked loop (PLL) systems
2011 IEEE Energy Conversion Congress and Exposition, 2011This paper studies two methods of addressing the DC component in phase-locked loop (PLL) systems. The DC component that may be actually present or may be generated by sensors, analog/digital converters or other signal conditioning systems, is a critical matter due to the fact that it causes low-frequency oscillations in the operation of PLL systems ...
Masoud Karimi-Ghartemani +3 more
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Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs
2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018This contribution aims to be a proof of the feasibility of a fully open architecture in Hardware Description Language of a Phase-Locked Loop (HDL-PLL) implemented in Field Programmable Gate Array (FPGA).Main parts of the system are the Phase-Frequency Detector (PFD) based on a Time-to-Digital Converter (TDC) and the Digital-Controlled Oscillator (DCO ...
Lusardi, N. +3 more
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