Results 131 to 140 of about 2,094 (182)
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Phase Locked Loop PLL-Based Frequency Synthesizers: A General Overview
Smart Innovation, Systems and Technologies, 2019This work summarizes the operating features for type II second-order Phase-Locked Loop (PLL)-based Frequency Synthesizers (FS) from the set of equations of linear dynamic modeling for defining the corresponding block level and system level transfer functions and developing the reference design equations for the Low Pass Filter (LPF) components sizing.
Agord M Pinto +2 more
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An Improved Linear Phase-Locked Loop (PLL) with notch Pre-filter
2021 IEEE 2nd China International Youth Conference on Electrical Engineering (CIYCEE), 2021Yun Xu
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Active Filter Circuits and Phase-Locked Loop (PLL)
2021Active filters and phase-locked loop (PLL) and its applications are discussed in this chapter. To get acquainted with the design of active filters and the applicability in instrumentation, low pass, high pass and band pass filters are explained. The frequency selection in audio or music systems is utmost important. The selection of lower and higher cut-
Shrikrishna Yawale, Sangita Yawale
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THE EFFECT OF THE FORCING FUNCTION ON DISRUPTION OF A PHASE-LOCKED LOOP (PLL)
International Journal of Bifurcation and Chaos, 2000In this paper we compare the disruption of a second-order type II phase-locked loop (PLL) by two different waveforms: a sinusoid and a sawtooth. The choice of these two waveforms results from a novel approach to the problem of determining an appropriate forcing function for studying the disruption of such systems.
S. M. Booker +3 more
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A new phase-locked loop (PLL) system
Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems. MWSCAS 2001 (Cat. No.01CH37257), 2002An enhanced phase-locked loop (PLL) system is presented and its properties and performance characteristics are investigated. Advantages of the proposed PLL structure over the conventional PLLs including its capability of direct estimation of amplitude and phase angle of its input signal, within a wide range of parameters, are demonstrated.
M. Karimi-Ghartemani, M.R. Iravani
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Development of low power Phase-Locked Loop (PLL) and PLL-based serial transceiver
Journal of Instrumentation, 2012The design and measurement results of a low power Phase-Locked Loop (PLL) and a PLL-based transceiver for applications in readout systems of particle physics detectors, designed and fabricated in a 0.35 ?m CMOS technology, are presented. The measurements show that the prototype PLL is fully functional and generates the clock signal in the frequency ...
J Moroń, M Firlej, M Idzik
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Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)
IEEE Transactions on Industrial Electronics, 1996Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters.
Fuminori Kobayashi +3 more
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Analysis of lock-loss events in discrete-time phase locked loop (PLL)
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., 2005Lock-loss phenomena were studied extensively for continuous-time phase locked loop (PLL), and closed form analytical expressions for the mean time to lose lock (MTLL) has been derived under the assumptions that the input is a phase modulated sine wave, and that the additive noise associated with the input can be added to the detector output.
Liran Brecher +2 more
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Phase Locked Loop (PLL) Design
2011The last building block covered in the book is the Phase Locked Loop (PLL), virtually used in every integrated communication front-end. The complexity of this system is high; therefore the first section is dedicated to the basic concepts related to both PLL system architectures and basic components.
Unai Alvarado +2 more
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Extended analysis of SSN effect on phase-locked loop (PLL) circuit
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity.
Joseph Kho +4 more
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