Results 131 to 140 of about 2,127 (187)
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Analysis of lock-loss events in discrete-time phase locked loop (PLL)
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., 2005Lock-loss phenomena were studied extensively for continuous-time phase locked loop (PLL), and closed form analytical expressions for the mean time to lose lock (MTLL) has been derived under the assumptions that the input is a phase modulated sine wave, and that the additive noise associated with the input can be added to the detector output.
Liran Brecher +2 more
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ASIC clock distribution using a phase locked loop (PLL)
[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 2002Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance. >
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Extended analysis of SSN effect on phase-locked loop (PLL) circuit
2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity.
Joseph Kho +4 more
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Computer simulation and parameter optimization of phase-locked loops (PLL)
SIMULATION, 1971The automatic control and simulation of phased- locked loops (PLL) is treated with particular em phasis on the use of analog and digital computer simulation techniques. The object is to obtain an adequate mathematical model for the PLL and then to use this model to optimize parameters and investi gate pull-in performance.
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Stabilizing Condition of Grid-Connected VSC as Affected by Phase Locked Loop (PLL)
IEEE Transactions on Power Delivery, 2022Zhengchun Du, Yujun Li
exaly
Synchronous reference frame single‐phase phase‐locked loop (PLL) algorithm based on half‐cycle DFT
IET Power Electronics, 2020Yezhao Liu, Tao Xia, Xu Zhang
exaly
Phase lock loops (PLLS) and methods of initializing PLLS
2021MAR WING, ZINGG RETO
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A study of third-order Phase-Locked Loop (PLL) systems
2008Master of Science (Consumer Electronics)
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Optimization analysis on the bandwidth algorithm for the phase-locked loop (PLL) in OTU
Optik, 2012Jianguo Yuan
exaly