Results 41 to 50 of about 20,323 (302)
Integrated Circuit Signal Generation and Detection Techniques for Microwave and Sub-Millimeter Wave Signals [PDF]
, 2012 The unabated reduction of device feature sizes in semiconductor processes, particularly in complementary metal-oxide semiconductor (CMOS) processes, has served as the enabling factor behind integrated electronic systems of ever increasing complexity and ...
Bohn, Florian
core +1 more source
Toward Tunable Magnetic Dirac Semimetals: Mn Doping of Cd3As2
Advanced Functional Materials, EarlyView.Dilute magnetic doping of topological semimetals offers a pathway to tune the topological phase via time reversal symmetry breaking. This is achieved by alloying the Dirac semimetal Cd3As2 with Mn via molecular beam epitaxy. Magnetotransport measurements provide preliminary evidence of changes to the electronic structure consistent with the emergence ...
Anthony D. Rice +10 more
wiley +1 more source
Linearized discrete-time model of higher order charge-pump PLLs
, 2011 European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, 29-31 August, 2011In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs).
Paul F. Curran +5 more
core +2 more sources
Advances in Sustainable and Wearable Textile Based Soft Robotics
Advanced Functional Materials, EarlyView.This Review examines advances in wearable textile‐based soft robotics, focusing on sustainable materials, integrated sensing, and scalable actuation. It discusses manufacturing and system integration across healthcare, assistive robotics, prosthetics, and human–machine interfaces, and highlights key challenges in circular design, including life‐cycle ...
Zahir Abbas +6 more
wiley +1 more source
Synchronization in networks of mutually delay-coupled phase-locked loops
New Journal of Physics, 2014 Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations.
Alexandros Pollakis +5 more
doaj +1 more source
All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
IET Circuits, Devices and Systems, 2021 Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
doaj +1 more source
, 2009 Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump ...
Tertinek, Stefan +3 more
core +2 more sources
Time‐Resolved Magnetization Switching Dynamics Driven by Orbital Torques
Advanced Functional Materials, EarlyView.Du et al. reveal nanosecond magnetization switching driven by orbital currents using time‐resolved Hall detection. The measurements separate domain nucleation from domain wall propagation and show that Joule heating strongly assists switching by lowering energy barriers.
Ao Du +4 more
wiley +1 more source
A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
Applied Sciences, 2019 In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
doaj +1 more source
IEEE Access, 2021 Synchronization is the key part to ensure the high performance of grid-connected systems. Phase-locked loop (PLL) is one of the most popular synchronizations due to its simple implementation and robustness under certain grid variations.
Jinming Xu +4 more
doaj +1 more source