Results 41 to 50 of about 4,408,411 (292)
A geometry‐reconfigured additive manufacturing strategy converts planar printed soft materials into soft compact neural probes with integrated hydrogel electrodes and microfluidic channels. The resulting NeuroMAP platform enables scalable multichannel recording, localized chemical delivery, stable in vivo electrophysiological recording, and reduced ...
Hyunjin Lee +15 more
wiley +1 more source
All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops
Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
doaj +1 more source
Designing Of Pulse Phase-Locked Loops
The paper considers pulse phase-locked loops (PPLL) in which switching of structure and parameters is used for improvement of dynamic and spectral characteristics Classification of existing switching algorithms is given in the paper.
A. A. Deryushev +2 more
doaj
Synchronization in networks of mutually delay-coupled phase-locked loops
Electronic components that perform tasks in a concerted way rely on a common time reference. For instance, parallel computing demands synchronous clocking of multiple cores or processors to reliably carry out joint computations.
Alexandros Pollakis +5 more
doaj +1 more source
An amphiphilic GOx nanoamphizyme was constructed by covalently introducing hydrophobic PPNI linkers onto GOx, enabling spontaneous self‐assembly into tunable nanoparticles. Mild crosslinking further stabilized the assemblies and enhanced catalytic performance and stability.
Yuan‐Hao Hsiao +4 more
wiley +1 more source
Frequency quantization in first-order digital phase-locked loops with frequency-modulated input [PDF]
Presented at the International Workshop on Nonlinear Maps and their Applications (NOMA '07), INSA, Toulouse, December 13-14, 2007Frequency granularity in a digital phase-locked loop arises from quantization in the number-controlled oscillator which ...
Tertinek, Stefan +2 more
core +1 more source
A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA
In this paper, a digital-to-time converter (DTC) based on the three delay lines (3D) Vernier principle is proposed and implemented with field programmable gate arrays (FPGAs).
Chenggang Yan, Chen Hu, Jianhui Wu
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Synchronization is the key part to ensure the high performance of grid-connected systems. Phase-locked loop (PLL) is one of the most popular synchronizations due to its simple implementation and robustness under certain grid variations.
Jinming Xu +4 more
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All‐epitaxial and scalable ferromagnetic/non‐magnetic Fe5−xGeTe2/WSe2 van der Waals (vdW) heterostructures exhibiting room‐temperature magnetism and perpendicular magnetic anisotropy (PMA) are realized. The system displays proximity‐tuned magnetic anisotropy, thickness‐dependent unconventional Hall effects, and temperature‐dependent sign reversal of ...
Hua Lv +15 more
wiley +1 more source
Reinvestigation of Single-Phase FLLs
Besides well-known phase-locked loops, frequency-locked loops (FLLs) are applicable to grid synchronization for grid-tied power converters. The models, principles, and algorithm structures of existing notch filter-based single-phase FLLs are often ...
Xiuqiang He, Hua Geng, Geng Yang
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