Results 21 to 30 of about 7,539 (261)

A Novel Hybrid Control Approach for Frequency and Voltage Regulation in IPT Systems

IET Power Electronics
The purpose of the inductive power transfer (IPT) system is to deliver sufficient power from the power supply to the load via a magnetic coupler. To optimise the efficiency, transmission power, and stability of IPT systems, it is essential to sustain the
Mohammadreza Kiyani, Seyed Ehsan Abdollahi, Seyedreza Abdollahi, Barmak Baigzadehnoe   +3 more
doaj   +1 more source

Impact of seismic activities on the optical synchronization system of the European X-ray Free-Electron Laser

High Power Laser Science and Engineering
This study investigates the influence of seismic activities on the optical synchronization system of the European X-ray Free-Electron Laser. We analyze the controller input/output data of phase-locked loops in length-stabilized links, focusing on the ...
Arne Grünhagen, Maximilian Schütte, Thorsten Lamb, Sebastian Schulz, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey, Holger Schlarb   +7 more
doaj   +1 more source

Impedance Modeling and Stability Analysis of the IMAF-PLL-Based NPC Three-Level LCL Grid-Connected Inverter

IEEE Access, 2020
The phase-locked loop of grid-connected inverters affects their output impedance characteristics and stability. Based on the NPC, three-level LCL grid-connected inverter, this article first analyzes the frequency characteristics of the improved moving ...
Wei Luo, Dafang Wei, Jianguo Jiang
doaj   +1 more source

Low Power Clock Generator Design With CMOS Signaling

IEEE Open Journal of the Solid-State Circuits Society, 2021
The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more
Yongping Fan, Ian A. Young
doaj   +1 more source

Purification and preparation of Marchantia polymorpha Auxin Response Factor 2 for phase separation studies

FEBS Open Bio, EarlyView.
We describe detailed protocols for the purification and preparation of Marchantia polymorpha Auxin Response Factor 2 (MpARF2). This protein is fused to an MBP solubility tag and an mNG fluorescent tag and is purified from Escherichia coli. The presented procedures make it possible to study MpARF2 assemblies, which could arise from phase separation ...
Bas Janssen, Robin Romein, Willy A. M. van den Berg, Simon Lindhoud, Jan Willem Borst, Carlo P. M. van Mierlo   +5 more
wiley   +1 more source

Mathematical models and simulations of phase noise in phase-locked loops [PDF]

Songklanakarin Journal of Science and Technology (SJST), 2007
Phase noises in Phase-Locked Loops (PLLs) are a key parameter for communication systems that contribute the bit-rate-error of communication systems and cause synchronization problems.
Sethapong Limkumnerd, Duangrat Eungdamrong   +1 more
doaj  

A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive

IEEE Access, 2022
The conventional phase-locked loops or frequency-locked loops should take time to calibrate the oscillator’s resonant frequency in a super-regenerative receiver (SRR) and severely disrupts the receiver’s operations.
Yadong Yin, Yitao Huang, Zhizhang Chen, Sio-Hang Pun, Yipeng Liao, Yueming Gao, Mang I. Vai   +6 more
doaj   +1 more source

Impact of Age on the Diagnostic Yield of Routine EEG in People With Childhood or Juvenile Absence Epilepsy: A Cross‐Sectional Study

Annals of Clinical and Translational Neurology, EarlyView.
ABSTRACT Background We aimed to identify the proportion of individuals with a confirmed diagnosis of childhood absence epilepsy (CAE) or juvenile absence epilepsy (JAE) who show a negative routine EEG (rEEG), and to determine the main factors associated with this finding.
Francesco Fortunato, Alessia Giugno, Miriam Sturniolo, Enrico Fratto, Pio Zoleo, Francesca Felicia Operto, Ilaria Sammarra, Antonio Gambardella   +7 more
wiley   +1 more source

All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

IET Circuits, Devices and Systems, 2021
Charge‐pump phase‐locked loop (CP‐PLL) is widely used to generate timing signals in systems on chips (SoCs). However, the number of cores embedded in SoCs, the limited I/O port resources and the cost of external test equipment lead to the increase of ...
Lanhua Xia, Jifei Tang
doaj   +1 more source

A Single-Event-Hardened Scheme of Phase-Locked Loop Microsystems for Aerospace Applications

Micromachines, 2022
In order to improve the ability of the phase-locked loop (PLL) microsystem applied in the aerospace environment to suppress the irradiation effect, this study presents an efficient charge pump hardened scheme by using the radiation-hardened-by-design ...
Qi Xiang, Hongxia Liu, Yulun Zhou
doaj   +1 more source