Results 261 to 270 of about 319,225 (348)
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IEEE Journal of Emerging and Selected Topics in Power Electronics, 2020
Phase-locked loop (PLL) with improper bandwidth could lead to potential instability issues for the grid-connected voltage-source converters (VSCs) under weak grid conditions.
Xing Li, Hua Lin
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Phase-locked loop (PLL) with improper bandwidth could lead to potential instability issues for the grid-connected voltage-source converters (VSCs) under weak grid conditions.
Xing Li, Hua Lin
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Modeling Phase-Locked Loop-Based Synchronization in Grid-Interfaced Converters
IEEE transactions on energy conversion, 2020Grid converters need a synchronization which is often a phase-locked loop (PLL) to get connected to the grid. In the literature, impedance-based models using small-signal technique have been widely utilized to describe the behaviors of PLL-synchronized ...
Zhixiang Zou, Marco Liserre
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IEEE transactions on industrial electronics (1982. Print), 2020
In power electronics and power systems, the dual-phase-locked loop (DPLL) is a well-accepted approach to maintain zero steady-state errors when subjecting to a frequency ramp input.
Huimin Wang +3 more
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In power electronics and power systems, the dual-phase-locked loop (DPLL) is a well-accepted approach to maintain zero steady-state errors when subjecting to a frequency ramp input.
Huimin Wang +3 more
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IEEE Transactions on Sustainable Energy, 2019
In the distributed power generation systems (DPGSs) based on the renewable energies, the stability and harmonics of the grid-connected inverter are seriously affected by the uncertainties of the grid at the point of common coupling (PCC).
Jinming Xu +3 more
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In the distributed power generation systems (DPGSs) based on the renewable energies, the stability and harmonics of the grid-connected inverter are seriously affected by the uncertainties of the grid at the point of common coupling (PCC).
Jinming Xu +3 more
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2024 Asia Pacific Conference on Innovation in Technology (APCIT)
Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector ( 100 ) comprising: means ( 10 ) for obtaining a first one of said frequency control signals (U, D)
van de Beek, R.C.H. +3 more
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Abstract of US2006164137 A phase locked loop comprising a phase detector ( 100 ) for determining a phase difference between a reference signal (Ref) and mutually phase shifted signals (I, Q) to generate frequency control signals (U, D), the phase detector ( 100 ) comprising: means ( 10 ) for obtaining a first one of said frequency control signals (U, D)
van de Beek, R.C.H. +3 more
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Lock Detection in Phase-Locked Loops
SIAM Journal on Applied Mathematics, 1992The phase quadrature lock detector is used extensively to detect phase lock in phase-locked loops (PLLs). However, this lock detector's relationship to PLL closed-loop dynamics has never been established. A new theory is presented, which accomplishes this for a specified class of PLLs.
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IEEE transactions on industry applications, 2020
The estimation of phase-angle, frequency, and amplitude are vital for the control of grid-connected power electronic systems in both single-phase and three-phase systems.
Srinivas Gude, C. Chu
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The estimation of phase-angle, frequency, and amplitude are vital for the control of grid-connected power electronic systems in both single-phase and three-phase systems.
Srinivas Gude, C. Chu
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Proceedings of the IEEE, 1975
A phase locked loop, (PLL), is basically a closed loop feedback system, the action of which is to lock or synchronise the frequency of a controlled oscillator to that of an incoming signal. Phase lock principles are by no means new, synchronous reception of radio signals using PLL techniques was described as early as 1932.
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A phase locked loop, (PLL), is basically a closed loop feedback system, the action of which is to lock or synchronise the frequency of a controlled oscillator to that of an incoming signal. Phase lock principles are by no means new, synchronous reception of radio signals using PLL techniques was described as early as 1932.
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Comparison and Simulation of Analog and Digital Phase Locked Loop
International Conference on Computing Communication and Networking Technologies, 2018This paper presents a comparative study between the two basic types of Phase locked loop (PLL) i.e. Analog phase locked loop (APLL) and Digital Phase locked loop (DPLL) and their implementation in Simulink.
Abhishek Godave +2 more
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Synchronizers based on carrier phase lock Loop and on symbol phase lock loop
2008 15th IEEE International Conference on Electronics, Circuits and Systems, 2008The symbol synchronizer recoveries the clock and after, with it, samples and retimes the data. We present two synchronizer groups, the first based on filter with carrier phase lock loop (CPLL) and the second based on symbol phase lock loop (SPLL). Each group has four prototypes namely the analog, the hybrid, the combinational and the sequential.
Reis, A.D. +3 more
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