Results 21 to 30 of about 4,808,695 (292)
Combined effect of loop delay and reference clock jitter in first-order digital bang-bang phase-locked loops [PDF]
, 2009 Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, 24-27 May 2009Recently, several digital phase-locked loops (DPLLs) have been demonstrated to achieve the jitter performance of traditional charge-pump ...
Tertinek, Stefan +3 more
core +1 more source
Research on frequency adaptive of fans based on harmonicextraction technology
Journal of Hebei University of Science and Technology, 2021 In order to solve the problem of voltage distortion and frequency fluctuation caused by harmonic interference of wind turbines which affects the stable operation of wind turbines connected to the grid,a frequency adaptive phase lock methodwas proposed ...
Xueyou ZHANG, Shan HE, Wenlong LI
doaj +1 more source
Carrier tracking algorithm based on joint acquisition of frequency locked loop and phase locked loop
MATEC Web of Conferences, 2017 Aiming at the problem of frequency step in the frequency lock loop (FLL) - phase lock loop (PLL) carrier tracking algorithm’s conversion state, presenting an improved algorithm: PLL and FLL joint acquisition to replace the single FLL acquires frequency ...
Gao Kang, Zhao Qiang, Peng BaoTong
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Energies, 2017 The control system of a doubly-fed adjustable-speed pumped-storage hydropower plant needs phase-locked loops (PLLs) to obtain the phase angle of grid voltage.
Wei Luo, Jianguo Jiang, He Liu
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Phase-Locked Loop with Inverse Tangent based Phase Detection
Advances in Electrical and Computer Engineering, 2021 In this paper, a novel closed-loop synchronization algorithm is proposed based on the linear phase angle detection. The linear phase detection is performed by the inverse tangent (atan2) trigonometric function, while the frequency tracking is performed
STOJIC, D.
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A Three-Phase Frequency-Fixed DSOGI-PLL With Low Computational Effort
IEEE Access, 2023 This paper offers a detailed analysis as well as a tuning and discretization approach of the presented frequency-fixed dual second order generalized integrator based phase-locked loop (FFDSOGI-PLL) for three-phase power systems.
Benjamin Hoepfner, Ralf Vick
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IEEE AccessTo handle the low frequency oscillations of the three-phase four-wire inverter grid-connected system caused by small phase-locked range, slow locking speed and large steady-state error of the traditional phase-locked loop, an improved phase-locked loop ...
Guoxuan Cui, Yanwen Wang, Liya Liu
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A design methodology to enable sampling PLLs to synthesise fractional-N frequencies [PDF]
, 2011 A novel design methodology is proposed to enable sampling phase-locked loops (SPLL) to synthesise fractional-N frequencies. To date, SPLL can only generate integer-N frequencies.
Xu, Tao +2 more
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Binary phase detector gain in bang-bang phase-locked loops with DCO jitter [PDF]
, 2010 Bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In the presence of jitter, the nonlinear loop is typically analyzed by linearizing the BPD and applying linear ...
Gleeson, James +5 more
core +1 more source
Enhanced Single-phase Phase Locked Loop based on Complex-Coefficient Filter [PDF]
, 2022 Complex coefficient filters (CCFs) are widely used for phase-locked loop (PLL) in three-phase power systems, while its usage is largely sparse in the single-phase domain.
Gautam, Samir +12 more
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