An Improved Single Phase-locked Loop Based on Synchronous Reference Frame
Kongzhi Yu Xinxi Jishu, 2019 Accurate tracking of phase angle, frequency and amplitude of the utility voltage is essential to ensure correct operation of grid connected inverters. The commonly used single phase-locked loop(SPLL) has poor dynamic characteristics due to the problem of
TANG Jianyu +4 more
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An Efficient Phase-Locked Loop for Distorted Three-Phase Systems
Energies, 2017 This paper proposed an efficient phase-locked loop (PLL) that features zero steady-state error of phase and frequency under voltage sag, phase jump, harmonics, DC offsets and step-and ramp-changed frequency. The PLL includes the sliding Goertzel discrete
Yijia Cao +4 more
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Theoretical Upper and Lower Limits for Normalized Bandwidth of Digital Phase-Locked Loop in GNSS Receivers. [PDF]
Sensors (Basel), 2023 Song YJ, Pany T, Won JH.
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Dynamical response and noise limit of a parametrically pumped microcantilever sensor in a Phase-Locked Loop. [PDF]
Sci Rep, 2023 Mouro J +3 more
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Estimator Parameter Tegangan Jaringan Tiga Fasa Berbasis D-SOGI PLL
Majalah Ilmiah Teknologi Elektro, 2017 Phase locked loop (PLL) adalah sebuah sistem umpan balik yang memegang peran penting dalam sistem-sistem konverter terkoneksi jaringan listrik. Fungsi utama PLL adalah mendapatkan beragam informasi parameter jaringan yaitu seperti phase dan magnitude ...
Iwan Setiawan +3 more
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Table-Based Adaptive Digital Phase-Locked Loop for GNSS Receivers Operating in Moon Exploration Missions. [PDF]
Sensors (Basel), 2022 Song YJ, Won JH.
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High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates
Journal of Electrical and Computer Engineering, 2015 Mathematical analysis and optimization of a carrier tracking loop are presented. Due to fast changing of the carrier frequency in some satellite systems, such as Low Earth Orbit (LEO) or Global Positioning System (GPS), or some planes like Unmanned ...
Amirhossein Fereidountabar +2 more
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A Low-Phase-Noise 8 GHz Linear-Band Sub-Millimeter-Wave Phase-Locked Loop in 22 nm FD-SOI CMOS. [PDF]
Micromachines (Basel), 2023 Kebe M, Sanduleanu M.
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Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process. [PDF]
Sensors (Basel), 2022 Zhao R, Zhang Y, Lv H, Wu Y.
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A 78.8-84 GHz Phase Locked Loop Synthesizer for a W-Band Frequency-Hopping FMCW Radar Transceiver in 65 nm CMOS. [PDF]
Sensors (Basel), 2022 Trinh VS, Nam H, Song JM, Park JD.
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