Results 161 to 170 of about 7,164 (210)

Lock Detection in Phase-Locked Loops

SIAM Journal on Applied Mathematics, 1992
The phase quadrature lock detector is used extensively to detect phase lock in phase-locked loops (PLLs). However, this lock detector's relationship to PLL closed-loop dynamics has never been established. A new theory is presented, which accomplishes this for a specified class of PLLs.
openaire   +2 more sources

Digital phase-locked loops

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
▪ Digital PLLs exploit CMOS scaling and allow accurate cancellation of fractional spurs and automatic bandwidth control ▪ In Bang-Bang DPLLs assisted by DTC, performance is only limited by DCO and DTC resolution ▪ Bang-Bang DPLLs assisted by DTC allow same phase-noise performance and fractionalspur level as standard DPLLs at much lower power ...
openaire   +1 more source

Hangup in Phase-Lock Loops

IEEE Transactions on Communications, 1977
A phase-lock loop occasionally will take a long time to settle to equilibrium. Phase dwells at a large error for a prolonged interval. This phenomenon has been dubbed "hangup." The periodic nature of phase detectors is responsible for hangup, which occurs near the reverse-slope, unstable null.
openaire   +1 more source

A novel three-phase software phase-locked loop based on frequency-locked loop and initial phase angle detection phase-locked loop

IECON 2012 - 38th Annual Conference on IEEE Industrial Electronics Society, 2012
This paper proposes a new three-phase software phase-locked loop (SPLL) which operates fast and accurately in unbalanced, polluted and frequency deviated circumstances. This new proposed SPLL consists of frequency-locked loop (FLL) and initial phase angle detection PLL. The FLL employs differential algorithm to detect frequency error which could immune
Liang Wang, Qirong Jiang, Lucheng Hong
openaire   +1 more source

False Lock and Bifurcation in the Phase Locked Loop

SIAM Journal on Applied Mathematics, 1987
New results are given on the phenomenon of false lock in phase locked loops (PLL). First, it is proved that for small values of closed loop gain \(\delta\), there is only one function \(\omega_ f(\delta)\) which represents the frequency error in a false locked Type 1 PLL.
openaire   +1 more source

Phase-locked loops

Soumyajit Mandal
exaly   +2 more sources

A digital loop filter for a Phase Locked Loop

2011 17th International Conference on Digital Signal Processing (DSP), 2011
Modern digital telecommunication and audio systems include a Digital Phase Locked Loop (D-PLL) in a form of a device or an algorithm. Wireless infrastructure, broadband wire-line networks and high end audio systems require very high performance PLLs.
openaire   +1 more source

On the Pull-In Range of Phase-Locked Loops

IEEE Transactions on Communications, 1975
The problem of determining the pull-in range of phaselocked loops is solved indirectly by evaluating the limit cycles of the loop in which the frequency error has a constant average. The analytical results derived here are in complete agreement with simulation results.
openaire   +1 more source

On Stochastic Phase-Lock Loop Solutions

IEEE Transactions on Communications, 1976
The solutions to stochastic first- and second-order phaselock loop differential equations are studied in the sense of the calculus of Ito and Stratonovich. The solutions are found to be both theoretically and experimentally invariant to the calculus used.
openaire   +1 more source

Phase-Locked Loops

2002
In this chapter we describe an important electronic circuit, the phase-locked loop (PLL). We first investigate the circuit’s dynamics without and with random perturbations, but in the absence of external forcing. Then we analyze the response of the circuit to noisy external signals, and we describe a method for extracting signals from the result.
Anatoli V. Skorokhod, Frank C. Hoppensteadt, Habib Salehi   +2 more
openaire   +1 more source