Results 101 to 110 of about 20,680 (162)

A new PLL architecture: the composite PLL

48th Midwest Symposium on Circuits and Systems, 2005., 2005
This paper presents a new PLL architecture that provides a larger frequency band of phase noise filtering in order to relax VCO building constraints. It consists in a classical PLL with a parallel band pass loop. This topology is called composite PLL.
V. Lagareste, F. Badets, D. Belot, Y. Deval, J.B. Begueret, P. Melchior   +5 more
openaire   +1 more source

PLLs, VCOs, and dividers

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Phase-locked loop (PLL) frequency synthesizers are critical building blocks for wireless transceivers. Frequency synthesis requires integrated oscillators and dividers that can provide superior phase noise performance at ultra-high frequencies. This session focuses on design of high-performance PLLs and building blocks, including voltage- and current ...
Fa Foster Dai, Howard C. Luong
openaire   +1 more source

SOGI PLL

2021
This note covers the operating principles of a Second-Order Generalized Integrator (SOGI) PLL and presents a possible implementation for digital power electronics controllers. Its implementation in Simulink and PLECS is available for download.
Antonin Stampbach, Nicolas Cherix
openaire   +1 more source

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL

IEICE Transactions on Electronics, 2005
This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics.
Takahito Miyazaki, Masanori Hashimoto, Hidetoshi Onodera   +2 more
openaire   +1 more source

Introduction to PLLs

2003
The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
openaire   +1 more source

Bang-bang digital PLLs

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
openaire   +1 more source

Hybrid PLL architectures and implementations

2018 IEEE Custom Integrated Circuits Conference (CICC), 2018
SSCS Webinar ...
openaire   +1 more source

Εφαρμογές PLL:

2009
Στο πρώτο κεφάλαιο γίνεται αναφορά στην έννοια του χάους και σύντομη ιστορική διαδρομή με βάση τους πρώτους θεωρητικούς επιστήμονες που ασχολήθηκαν με αυτό. Στην συνέχεια περιγράφονται τα δυναμικά κυκλώματα και η χαοτική συμπεριφορά των ηλεκτρικών κυκλωμάτων.
openaire   +1 more source

Performance enhancement of DSOGI-PLL with a simple approach in grid-connected applications

Energy Reports, 2022
Hulusi Karaca, Fehmi Sevilmis
exaly  

Analog Techniques and PLLs

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
Vadim Gutnik, Stefan Heinen
openaire   +1 more source