Results 211 to 220 of about 40,201 (266)
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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Phase-locked loop (PLL) frequency synthesizers are critical building blocks for wireless transceivers. Frequency synthesis requires integrated oscillators and dividers that can provide superior phase noise performance at ultra-high frequencies. This session focuses on design of high-performance PLLs and building blocks, including voltage- and current ...
Fa Foster Dai, Howard C. Luong
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Phase-locked loop (PLL) frequency synthesizers are critical building blocks for wireless transceivers. Frequency synthesis requires integrated oscillators and dividers that can provide superior phase noise performance at ultra-high frequencies. This session focuses on design of high-performance PLLs and building blocks, including voltage- and current ...
Fa Foster Dai, Howard C. Luong
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IEICE Transactions on Electronics, 2005
This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics.
Takahito Miyazaki +2 more
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This paper discusses performance prediction of clock generation PLLs using a ring oscillator based VCO (RingVCO) and an LC oscillator based VCO (LCVCO). For clock generation, we generally design PLLs using RingVCOs because of their superiority in tunable frequency range, chip area and power consumption, in spite of their poor noise characteristics.
Takahito Miyazaki +2 more
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2003
The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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2009
Στο πρώτο κεφάλαιο γίνεται αναφορά στην έννοια του χάους και σύντομη ιστορική διαδρομή με βάση τους πρώτους θεωρητικούς επιστήμονες που ασχολήθηκαν με αυτό. Στην συνέχεια περιγράφονται τα δυναμικά κυκλώματα και η χαοτική συμπεριφορά των ηλεκτρικών κυκλωμάτων.
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Στο πρώτο κεφάλαιο γίνεται αναφορά στην έννοια του χάους και σύντομη ιστορική διαδρομή με βάση τους πρώτους θεωρητικούς επιστήμονες που ασχολήθηκαν με αυτό. Στην συνέχεια περιγράφονται τα δυναμικά κυκλώματα και η χαοτική συμπεριφορά των ηλεκτρικών κυκλωμάτων.
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Hybrid PLL architectures and implementations
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018SSCS Webinar ...
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2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 2007
Vadim Gutnik, Stefan Heinen
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Vadim Gutnik, Stefan Heinen
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Performance enhancement of DSOGI-PLL with a simple approach in grid-connected applications
Energy Reports, 2022Hulusi Karaca, Fehmi Sevilmis
exaly