Results 261 to 270 of about 179,155 (337)

Comparison of PLL-Based and PLL-Less Vector Current Controllers

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2022
This paper presents a detailed and rigorous comparison between two vector current control (VCC) approaches for voltage source converters (VSC). A PLL-less VCC (also called the direct power control) has recently been proposed in several major publications with the assumption that it will improve the performance of conventional PLL-based VCC during weak ...
S. Milad Hoseinizadeh, Saeed Ouni, Houshang Karimi, Masoud Karimi-Ghartemani, Kuo Lung Lian   +4 more
openaire   +2 more sources

Sensorless Control of PMSM Drives Using Reduced Order Quasi Resonant-Based ESO and Newton–Raphson Method-Based PLL

IEEE transactions on power electronics, 2023
This article proposes a novel sensorless control strategy for permanent magnet synchronous motor drives using reduced order quasi resonant-based extended state observer (ROQR-ESO) and Newton–Raphson method-based phase-locked loop (NRM-PLL).
Shuo Chen, Wen Ding, Ruiming Hu, Xiang Wu, Shuai Shi   +4 more
semanticscholar   +1 more source

Constant-Coupling-Effect-Based PLL for Synchronization Stability Enhancement of Grid-Connected Converter Under Weak Grids

IEEE transactions on industrial electronics (1982. Print), 2023
The phase-locked loop (PLL)-caused couplings on the grid-connected converter (GCC) are strengthened by increasing its bandwidth and then incur synchronization instability.
X. Lin, Ruoxue Yu, Jingrong Yu, H. Wen
semanticscholar   +1 more source

PLL- and FLL-Based Speed Estimation Schemes for Speed-Sensorless Control of Induction Motor Drives: Review and New Attempts

IEEE transactions on power electronics, 2022
Phase-locked loops (PLLs) and frequency-locked loops (FLLs) are of importance in power and energy applications. Both technologies have been introduced to speed-sensorless- controlled motor drives, and increasing applications of PLLs and FLLs for speed ...
Huimin Wang, Yongheng Yang, X. Ge, Y. Zuo, Yan Yue, Songtao Li   +5 more
semanticscholar   +1 more source

Impedance Characteristic Analysis and Stability Improvement Method for DFIG System Within PLL Bandwidth Based on Different Reference Frames

IEEE transactions on industrial electronics (1982. Print), 2023
The phase-locked loop (PLL) will have a negative impact on the stability of doubly fed induction generators (DFIG) system under inductive weak grid. Some PLL-less methods have been presented to remove the PLL such as switching the synchronous reference ...
Bin Hu, H. Nian, Meng Li, Yuming Liao, Jun Yang, Haolin Tong   +5 more
semanticscholar   +1 more source

Estimated Position Error Suppression Using Novel PLL for IPMSM Sensorless Drives Based on Full-Order SMO

IEEE transactions on power electronics, 2022
To heighten the position estimation accuracy of sensorless control of interior permanent magnet synchronous motor (IPMSM), an improved full-order sliding mode observer (FSMO) based on novel phase-locked loop (PLL) is proposed in this article. By contrast
Zhonggang Yin, Yanping Zhang, Xinping Cao, D. Yuan, Jing Liu   +4 more
semanticscholar   +1 more source

Generalized Swing Equation and Transient Synchronous Stability With PLL-Based VSC

IEEE transactions on energy conversion, 2022
With widespread application of voltage source converter (VSC) as a key energy-conversion power electronic device by using the phase-locked loop (PLL) technique for synchronization, the system dynamics has become much complicated.
Rui Ma, Jinxin Li, J. Kurths, Shi-jie Cheng, Mengyuan Zhan   +4 more
semanticscholar   +1 more source

Stability Analysis of the Grid-Connected Inverter Considering the Asymmetric Positive-Feedback Loops Introduced by the PLL in Weak Grids

IEEE transactions on industrial electronics (1982. Print), 2022
The stability of the grid-connected inverter (GCI) system in weak grids is deteriorated due to the asymmetric positive-feedback loops (APFLs) introduced by the phase-locked loop (PLL) structure.
Chunming Tu, Jiayuan Gao, Fan Xiao, Qi Guo, Fei Jiang   +4 more
semanticscholar   +1 more source

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO

IEEE Journal of Solid-State Circuits, 2021
This work presents a 6-GHz low-jitter and high figure-of-merit (FoM) fractional- $N$ phase-locked loop (PLL). It uses a digital-to-time converter (DTC)-based sampling PLL architecture.
Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, S. Son, T. Cho   +8 more
semanticscholar   +1 more source

A Straightforward Quadrature Signal Generator for Single-Phase SOGI-PLL With Low Susceptibility to Grid Harmonics

IEEE transactions on industrial electronics (1982. Print), 2022
Suppressing the negative effects of grid voltage harmonics on the estimated frequency of a phase-locked loop (PLL) is a challenge in literature. This article proposes an easy-to-implement quadrature signal generator (QSG) to attenuate the oscillations on
S. Mohamadian, Hamidreza Pairo, A. Ghasemian   +2 more
semanticscholar   +1 more source