Results 291 to 300 of about 179,155 (337)
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A new FM modulator using phase unstable PLL (PU-PLL)
Proceedings of the IEEE, 1981A phase-locked loop (PLL) with a second-order low-pass filter can oscillate with the frequency nearly equal to the filter cutoff. By modulating the amplitude of the oscillation, a stable frequency modulated signal can be obtained at the output of a voltage-controlled oscillator (VCO).
T. Takagi, J. Ohguchi
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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of −256 dB
IEEE Journal of Solid-State Circuits, 2020An active-mixer-adopted sub-sampling phase-locked loop (AMASS-PLL) is presented that replaces the passive-mixer-like sample-and-hold switches and charge pump (CP) of a sub-sampling PLL (SSPLL) with an active-mixer and $g_{m}$ -cell, which reduces ...
Dhon-Gue Lee, P. Mercier
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Nonlinear Analysis of PLL Damping Characteristics in Weak-Grid-Tied Inverters
IEEE Transactions on Circuits and Systems - II - Express Briefs, 2020Under weak grid scenarios, the widely adopted synchronous reference frame phase-locked loop (SRF-PLL) exhibits complex behavior due to the possible grid phase or frequency disturbances.
Jiantao Zhao, Meng Huang, X. Zha
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PLL system for harmonic analysis
2011 10th International Conference on Environment and Electrical Engineering, 2011PLL principles system and its applications in harmonic analysis are firstly discussed and then integrated presenting methods to increase the PLL-based instrumentation efficiency. A comparison between the performance of systems before and after the application of these methods are shown to validate the efficiency o f the proposed methods.
ANTONELLI A +2 more
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IEEE transactions on industry applications, 2018
Phase-locked loop (PLL) is commonly used for three-phase grid-connected inverters to obtain the information of grid synchronization, and PLL dynamics are the key factors for stable operation of the inverters.
Xueguang Zhang +4 more
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Phase-locked loop (PLL) is commonly used for three-phase grid-connected inverters to obtain the information of grid synchronization, and PLL dynamics are the key factors for stable operation of the inverters.
Xueguang Zhang +4 more
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A comparative study between Fractional-N PLL and Flying-Adder PLL
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency.
Liming Xiu, Chen-Wei Huang, Ping Gui
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2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2017
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain.
Yajun He +7 more
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This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain.
Yajun He +7 more
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2003
The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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2003
We have developed phase noise models for ring oscillators and applied our theoretical analysis to an example design of a ring oscillator. In a real system, a VCO is rarely used as a stand-alone component, because its output frequency is not well controlled.
Liang Dai, Ramesh Harjani
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We have developed phase noise models for ring oscillators and applied our theoretical analysis to an example design of a ring oscillator. In a real system, a VCO is rarely used as a stand-alone component, because its output frequency is not well controlled.
Liang Dai, Ramesh Harjani
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