Results 11 to 20 of about 149,980,641 (289)

Managing a reconfigurable processor in a general purpose workstation environment [PDF]

, 2003
This dissertation considers the problems associated with using Field Programmable Logic (FPL) within a processor to accelerate applications in the context of a general purpose workstation, where this scarce resource will need to be shared fairly and ...
Dales, Michael Winston, Dales, M., Michael Dales   +2 more
core   +10 more sources

Processor-In-Loop hardware setup.

, 2022
Processor-In-Loop hardware setup.
Nik Rumzi Bin Nik Idris (12883823), Muhammad Abbas Abbasi (12883826), Waqas Anjum (8415186), Abdul Rashid Husain (8415189), Hasan Alqaraghuli (8415198)   +4 more
core   +1 more source

Methodology for the formal specification of RTL RISC processor designs (with particular reference to the ARM6) [PDF]

, 2003
Due to the need to meet increasingly challenging objectives of increasing performance, reducing power consumption and reducing size, synchronous processor core designs have been increasing significantly in complexity for some time now.
Schostak, Daniel Paul
core   +7 more sources

Closed-loop controller design, stability analysis and hardware implementation for fractional neutron point kinetics model

Nuclear Engineering and Technology, 2021
The aim of this work is the analysis, design and hardware implementation of the fractional-order point kinetics (FNPK) model along with its closed-loop controller. The stability and closed-loop control of FNPK models are critical issues.
Vishwesh A. Vyawahare, G. Datkhile, P. Kadam, G. Espinosa-Paredes   +3 more
doaj   +1 more source

Modelling of Real Time Units in the Verification and Validation Process of Satellite Systems [PDF]

INCAS Bulletin
Verification and Validation (V&V) methodologies are essential to ensure the correct operations of control algorithms of the embedded software during a satellite mission.
Marius-Daniel MARINESCU, Stefan-Florin GRIGORE, Teodor-Andrei CRISTEA, Florin TACHE, Lorenzo CERCOS PITA, Samuel MUNOZ-CABALLERO, Germán MORENO ESCUDERO   +6 more
doaj   +1 more source

Wonderful news - As of June 2023 Scots poet and former Makar Jackie Kay is a patron of Loop!!!

, 2023
Jackie Kay was born and brought up in Scotland. She is the author of—among other books—The Adoption Papers, which won the Forward Prize, Red Dust Road, winner of the Scottish Book of the Year Award, Trumpet, and the Costa-shortlisted Fiere.
The LOOP team
core   +1 more source

Prelude to Simulations of Loop Quantum Gravity on Adiabatic Quantum Computers

Frontiers in Astronomy and Space Sciences, 2021
The article addresses the possibility of implementing spin network states, used in the loop quantum gravity approach to Planck scale physics on an adiabatic quantum computer.
Jakub Mielczarek
doaj   +1 more source

Parallelization of the Traveling Salesman Problem by Clustering its Nodes and Finding the Best Route Passing through the Centroids

Applied Computer Systems, 2023
A method of heuristically solving large and extremely large traveling salesman problems is suggested. The solver is a specific genetic algorithm producing approximately shortest routes the fastest of known heuristics without losing much in accuracy.
Romanuke Vadim
doaj   +1 more source

Design and implementation of energy reshaping based fuzzy logic control for optimal power extraction of PMSG wind energy converter

Frontiers in Energy Research, 2022
Given the greater penetration of wind power, the impact of wind generators on grid electricity reliability imposes additional requirements. One of the most common technologies in wind power generating schemes is the permanent magnet synchronous generator
Ashish Jaiswal, Youcef Belkhier, Subhash Chandra, Anurag Priyadarshi, Mohit Bajaj, Mukesh Pushkarna, Elmazeg Elgamli, Mokhtar Shouran, Salah Kamel   +8 more
doaj   +1 more source

Critical Section Overhead Reduction for OpenMP Program by Nesting a Serial Loop to Increase Task Granularity of Parallel Loop

Jurnal RESTI (Rekayasa Sistem dan Teknologi Informasi), 2022
This paper presents a simple method to reduce performance loss due to a parallel program's massive critical sections of parallel numerical integration.
Adnan Adnan, Intan Sari Areni, Zulkifli Tahir   +2 more
doaj   +1 more source