Results 71 to 80 of about 15,659 (313)
FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods
Background Likelihood (ML)-based phylogenetic inference has become a popular method for estimating the evolutionary relationships among species based on genomic sequence data.
Bakos Jason D, Zierke Stephanie
doaj +1 more source
Portable Stimulus Scenarios Specification for RISC-V Processor Modules
The thesis is focused on the design and implementation of the portable stimulus verification scenarios for selected Berkelium processor modules based on RISC-V architecture from Codasip.
Bardonek, Petr
core
Protein aggregates threaten proteostasis and cell health. In human cells, Hsp70–J‐domain protein‐based disaggregases remove aggregates, but how they assemble remains unclear. Our biochemical findings show that DNAJA2‐ and DNAJB1‐containing disaggregase scaffolds enhance luciferase aggregate targeting, and that Hsp70 recruitment by both J‐domain ...
Anna Szlachcic, Nadinath B. Nillegoda
wiley +1 more source
Design and Implementation of HD Video Encoding System Based on HDMI
Focus on the problem that TI’s dedicated video processor TMS320DM8148 cannot directly collect video data from HDMI interface, this paper presents a video coding system based on H.264.The system used DSP+FPGA architecture, FPGA is responsible for ...
Gao Wanjia +3 more
doaj +1 more source
Online Track Processor for the CDF Upgrade
A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the Collider Detector at Fermilab (CDF) upgrade. This processor identifies high-transverse- momentum ( 1 5 GeV/c) charged particles in the new central outer ...
K. Bloom +55 more
core +1 more source
FLARE: A design environment for FLASH-based space applications [PDF]
Designing a mass-memory device (i.e., a solid-state recorder) is one of the typical issues of mission-critical space system applications. Flash-memories could be used for this goal: a huge number of parameters and trade-offs need to be explored.
Stefano Di Carlo +8 more
core +1 more source
Reconstructing enzyme evolution by protein engineering
Natural enzyme evolution can be retraced by protein engineering methods such as directed evolution, rational design, and ancestral sequence reconstruction. These approaches reveal how enzymes emerged from ligand‐binding scaffolds, developed varying substrate preferences, formed oligomeric complexes, adapted to environmental changes, and evolved novel ...
Lukas Drexler +2 more
wiley +1 more source
Increasing the number of transistors to enhance the performance of processors leads to overheating, creating a need for cooling. Traditional cooling methods with copper pipes are becoming outdated and insufficient, prompting the development of ...
Fatih Uysal, Sinan Çobaner
doaj +1 more source
The present work addresses the development of a test-bench for the embedded implementation, validity, and testing of the recently proposed Improved Elephant Herding Optimization (iEHO) algorithm, applied to the acoustic localization problem.
Sérgio D. Correia +3 more
doaj +1 more source
Array processor architecture connection network
A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors.
Lundstrom, Stephen F. +2 more
core

