Results 141 to 150 of about 256 (160)
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An energy efficient multi-rate QC-LDPC decoder
2017 International Conference on Technological Advancements in Power and Energy ( TAP Energy), 2017This paper introduces, an energy efficient multirate decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. To achieve good error correcting performance with lower complexity, an improved normalized min-sum algorithm with row-merge scheme is adopted.
Michaelraj Kingston Roberts +1 more
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A new construction of UEP QC-LDPC codes
2010 IEEE International Symposium on Information Theory, 2010In this paper, a new construction of quasi-cyclic low-density parity-check (QC-LDPC) codes for unequal error protection (UEP) is proposed. We first give a new class of UEP block codes. QC-LDPC codes with binomial-term parity-check matrices which can avoid girths less than 8 and achieve an enlarged upper bound on the minimum distance are also introduced.
Chi-Jen Wu +2 more
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A High-Throughput QC-LDPC Encoder
2023 Asia Communications and Photonics Conference/2023 International Photonics and Optoelectronics Meetings (ACP/POEM), 2023Yifan Ding, Qiang Cao, Jie Yao
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Row Division Method to Generate QC-LDPC Codes
2009 Fifth Advanced International Conference on Telecommunications, 2009To cut down the hardware implementation cost this paper presents an efficient method to construct large girth Quasi-Cyclic low density parity check (QC-LDPC) codes. The row groups are paired two times the row weight, which has the complexity as compared to the connection of individual columns and rows.
Abid Yahya +3 more
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Automatic implementation of low-complexity QC-LDPC encoders
2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi ...
Tzimpragos G. +3 more
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QC-LDPC Decoding Architecture based on Stride Scheduling
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors ...
Bongjin Kim, In-Cheol Park
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High-Throughput FPGA-Based QC-LDPC Decoder Architecture
2015 IEEE 82nd Vehicular Technology Conference (VTC2015-Fall), 2015We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a binary Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain.
Swapnil Mhaske +4 more
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5G NR: Enhanced QC-LDPC Code Development
2023 International Conference on Power Energy, Environment & Intelligent Control (PEEIC), 2023Asha. KS +2 more
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QC-LDPC codes from various Golomb Rulers
2023 14th International Conference on Information and Communication Technology Convergence (ICTC), 2023Daekyeong Kim +2 more
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Configurable Universal QC-LDPC Encoder Architecture Design
2022 IEEE 5th International Conference on Electronic Information and Communication Technology (ICEICT), 2022Mingbo Hao +3 more
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