Results 141 to 150 of about 1,775 (200)

Multi-Rate QC-LDPC Encoder

2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, 2009
A multi-rate memory-efficient encoder for low-density parity-check (LDPC) codes is proposed in this paper based on shift-register-adder-accumulator (SRAA). The SRAA algorithm simplifies the encoder computation module and reduces the complexity of the operation. The LDPC code generator matrix is constructed by lots of quasi-cyclic square matrices in the
Huxing Zhang, Hongyang Yu
openaire   +1 more source

Compressing construction of QC-LDPC codes

2008 11th IEEE Singapore International Conference on Communication Systems, 2008
Two compressing construction methods of quasi-cyclic LDPC (QC-LDPC) codes are proposed, which can be called recursive-compressing and single-compressing respectively. Selecting a good QC-LDPC code as the Mother, the son codes constructed through the compressing methods are still good codes, i.e., have high girth and few short cycles, moreover, they ...
null Shuqi Sun, null Wuyang Zhou
openaire   +1 more source

3GPP2/802.20 RC/QC-LDPC encoding

2010 European Wireless Conference (EW), 2010
Rate-Compatible/Quasi-Cyclic LDPC codes are gaining importance because of their tradeoff between performance and simplicity. For these reasons, RC/QC LDPC codes have been included in several recent standards such as 802.20 and 3GPP2. General proposals for hardware encoding of this kind of LDPC codes either consume a lot of area to increase the ...
Jesus M. Perez, Victor Fernandez
openaire   +1 more source

Shortening for irregular QC-LDPC codes

IEEE Communications Letters, 2009
Shortening is a technique to obtain codes of shorter length and lower rate from a given LDPC code by putting infinite reliability on some variable nodes, whose positions are assumed to be available to both encoder and decoder. In this paper, we propose a shortening algorithm suitable for irregular QC-LDPC codes. The efficiency of the proposed algorithm
Xiaojian Liu, Xiaofu Wu, Chunming Zhao
openaire   +1 more source

Efficient Decoder Implementation for QC-LDPC Codes

2006 International Conference on Communications, Circuits and Systems, 2006
Channel coding is an important building block in communication systems. Low-density parity-check codes is one kind of prominent error correcting codes being considered in next generation industry standards. This paper presents a memory efficient, very high speed decoder architecture suited for quasi-cyclic low-density parity-check codes using modified ...
Jin Sha, Minglun Gao, Zhongjin Zhang, Li li, Zhongfeng Wang   +4 more
openaire   +1 more source

Construction of high-girth QC-LDPC codes

2008 5th International Symposium on Turbo Codes and Related Topics, 2008
We describe a hill-climbing algorithm that constructs high-girth quasi-cyclic low-density parity check (QC-LDPC) codes. Given a desired girth, the algorithm can find QC-LDPC codes of shorter block-length in much less time compared with the previously proposed ldquoguess-and-testrdquo algorithm.
null Yige Wang, J.S. Yedidia, S.C. Draper   +2 more
openaire   +1 more source

A Low Complexity Parallel QC-LDPC Encoder

2021 IEEE MTT-S International Wireless Symposium (IWS), 2021
In this paper, a low complexity parallel QC (quasi-cyclic)-LDPC (low-density parity-check) Codes encoding algorithm and encoder architecture is introduced. In traditional encoder architectures, the complexity of multiplication operation of information sequence and generator matrix is very high.
Xiaoxia Yao, Lintao Li, Jihong Liu, Qian Li   +3 more
openaire   +1 more source

High-throughput DOCSIS upstream QC-LDPC decoder

2014 48th Asilomar Conference on Signals, Systems and Computers, 2014
The newly released Data Over Cable Service Interface Specification (DOCSIS) 3.1 standard enables gigabit-speed broadband connection over cable television network. The main challenge at the upstream receiver is a computationally intensive LDPC decoder which need to achieve the 1Gbps throughput with low block error rates.
Michael Wu, Bei Yin, Eric Miller, Chris Dick, Joseph R. Cavallaro   +4 more
openaire   +1 more source

Design QC-LDPC coder based on FPGA

2011 International Conference on Electrical and Control Engineering, 2011
In this paper we study some fundamental properties of QC-LDPC code, we use a recursive compression algorithm to optimize the structure of QC-LDPC code, it can effectively reduce the coding complexity, save the space which is used to storage QC-LDPC code, and don't need to reduce its error correction performance.
Mingchuan Meng, He Guan, Jing Li
openaire   +1 more source

Construction of high-rate QC-LDPC codes

The 2011 International Conference on Advanced Technologies for Communications (ATC 2011), 2011
In this paper, we construct high-rate quasi-cyclic low-density parity-check (QC-LDPC) codes with girth-10 based on shortened array codes. First, we derive analytic results on the maximum number of columns for shortened array codes of different girths. A code construction method inspired by the analysis is proposed for column-weight-three codes and is ...
null Xu Chen, Francis C.M. Lau
openaire   +1 more source