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Design and Implementation of a Universal QC-LDPC Encoder
2016This paper designed a programmable processor based on multiple instruction multiple data (MIMD) structure, to realize the quasi-cyclic low density parity check code (QC-LDPC) coding algorithm for the wireless LAN (WLAN) and the worldwide interoperability for microwave access (WIMAX).
Qian Yi, Han Jing
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Adapted scheduling of QC-LDPC decoding for multistandard receivers
2012 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC), 2012Wireless and PLC standards have to cope with noisy channels. The advanced FEC codes like LDPC and turbo codes are the most competitive ones. Multi-standards devices (such as mobile phones with cellular and WiFi) are becoming more and more attractive but raise the issue of duplicating hardware.
Dion, Jean +4 more
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High-throughput DOCSIS upstream QC-LDPC decoder
2014 48th Asilomar Conference on Signals, Systems and Computers, 2014The newly released Data Over Cable Service Interface Specification (DOCSIS) 3.1 standard enables gigabit-speed broadband connection over cable television network. The main challenge at the upstream receiver is a computationally intensive LDPC decoder which need to achieve the 1Gbps throughput with low block error rates.
Michael Wu 0001 +4 more
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QC-LDPC Decoding Architecture based on Stride Scheduling
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011In this paper, an area-efficient decoder architecture is proposed for the quasi-cyclic low-density parity check (QC-LDPC) codes specified in the WiMAX 802.16e standard. In order to achieve low area and maximize hardware utilization, the decoder utilizes 4 decoding function units, which is the greatest common divisor of the expansion factors ...
Bongjin Kim, In-Cheol Park
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Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021In various wireless communication standards, such as Wi-Fi, WiMAX, and 5G standards, QC-LDPC decoders are required to decode a codeword of variable length. Part of the decoder is in idle if the length of codeword is not the maximum. A reconfigurable cyclic shifter is a key element of a QC-LDPC decoder. If the shifter can only shift one input at a time,
Hing-Mo Lam +5 more
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Memory compact high-speed QC-LDPC decoder
2017 IEEE International Conference on Signal Processing, Communications and Computing (ICSPCC), 2017In this paper, compact memory strategies for partially parallel Quasi-cyclic LDPC (QC-LDPC) decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle,
Tianjiao Xie +3 more
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A flexible and overlapped QC-LDPC decoder
2008 9th International Conference on Signal Processing, 2008There are many low-density parity-check (LDPC) decoder architectures in the literature most of which are based on structured codes. Besides been specific to a particular class of codes, suggested architectures are limited in scalability. The major challenge in decoder design and implementation is the consideration of several strongly interrelated ...
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A flexible decoder IC for WiMAX QC-LDPC codes
2008 IEEE Custom Integrated Circuits Conference, 2008A programmable and power-efficient decoder IC employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented. The iterative decoder can be reconfigured to decode all the QC-LDPC codes defined in the Mobile WiMAX standard.
Tzu-Chieh Kuo, Alan N. Willson Jr.
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Protograph design for QC LDPC codes with large girth
2010 International Conference on Information and Communication Technology Convergence (ICTC), 2010In this paper, all subgraph patterns of protographs which prevent quasi-cyclic (QC) low-density parity-check (LDPC) codes from having large girth are searched in allowance with multiple edges based on graph theoretic approach. A systematic construction of protograph with multiple edges using combinatorial design is proposed for QC LDPC codes with girth
Hosung Park +3 more
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Automatic implementation of low-complexity QC-LDPC encoders
2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2013Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi ...
Georgios Tzimpragos +3 more
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