Results 41 to 50 of about 69,988 (217)
On the Girth of Tanner (3, 13) Quasi-Cyclic LDPC Codes
IEEE Access, 2019 Girth is an important structural property of low-density parity-check (LDPC) codes. Motivated by the works on the girth of Tanner (3, 5), (3, 7), (3, 11), and (5, 7) quasi-cyclic (QC) LDPC codes, we, in this paper, study the girth of Tanner (3, 13) QC ...
Hengzhou Xu +4 more
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An Efficient Construction Method for Quasi-Cyclic Low Density Parity Check Codes
IEEE Access, 2017 In this paper, we propose an optimized belief propagation (OBP) based progressive edge-growth (PEG) method for constructing quasi-cyclic low density parity check (QC-LDPC) codes. In this proposed method, Tanner graphs are built by progressively appending
Yiming Lei, Mingke Dong
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IEEE Access, 2021 Multitype quasi-cyclic (QC) low-density parity-check (LDPC) codes are a class of protograph LDPC codes lifted cyclically from protographs with multiple edges, represented by two weight and slope matrices.
Farzaneh Abedi, Mohammad Gholami
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From Product Codes to Structured Generalized LDPC Codes [PDF]
, 2010 Product codes, due to their relatively large minimum distance, are often seen as a natural solution for applications requiring low error floors.
Paolini, Enrico +10 more
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Tanner
IEEE Access, 2019 Girth plays an important role in the design of low-density parity-check (LDPC) codes. Motivated by the works on the girth of some classes of Tanner quasi-cyclic (QC) LDPC codes, e.g., Tanner (3, 5), (3, 7), (3, 11), and (5, 7) codes, we, in this paper ...
Hengzhou Xu +4 more
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Ldpc Code Construction using Randomly Permutated Copies of Parity Check Matrix [PDF]
مجلة جامعة النجاح للأبحاث العلوم الطبيعية, 2018 A construction technique is proposed for low-density parity check (LDPC) codes. It uses a base parity check matrix designed from a ran-dom or constructed construction method as Gallager or Quasi-Cyclic LDPC (QC-LDPC) codes in sequence to get codes with ...
Amr lulu, Ammar Abu-Hudrouss
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Low latency low power bit flipping algorithms for LDPC decoding [PDF]
, 2010 Low Density Parity Check (LDPC) codes have been adopted in a number of wired and wireless communication standards due to their improved error correcting ability and relatively simple decoder structure.
Koçak, T +11 more
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LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA
Xibei Gongye Daxue Xuebao, 2019 A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase ...
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An LDPC Decoder Architecture forWireless Sensor Network Applications [PDF]
, 2012 The pervasive use of wireless sensors in a growing spectrum of human activities reinforces the need for devices with low energy dissipation. In this work, coded communication between a couple of wireless sensor devices is considered as a method to reduce
Biroli, Andrea Dario Giancarlo +5 more
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A massively parallel implementation of QC-LDPC decoder on GPU [PDF]
2011 IEEE 9th Symposium on Application Specific Processors (SASP), 2011 The graphics processor unit (GPU) is able to provide a low-cost and flexible software-based multi-core architecture for high performance computing. However, it is still very challenging to efficiently map the real-world applications to GPU and fully utilize the computational power of GPU. As a case study, we present a GPU-based implementation of a real-
Guohui Wang +3 more
openaire +1 more source