Results 21 to 30 of about 139,535 (196)
On the lifting degree of girth-8 QC-LDPC codes [PDF]
The lifting degree and the deterministic construction of quasi-cyclic low-density parity-check (QC-LDPC) codes have been extensively studied, with many construction methods in the literature, including those based on finite geometry, array-based codes, computer search, and combinatorial techniques.
Haoran Xiong+3 more
openalex +3 more sources
The design of structured LDPC codes with algorithmic graph construction [PDF]
Low-Density Parity-Check (LDPC) codes are among the most effective modern error-correcting codes due to their excellent correction performance and highly parallel decoding scheme.
Wojciech Sułek
doaj +1 more source
Full-Length Row-Multiplier QC-LDPC Codes With Girth Eight and Short Circulant Sizes
As a special case of a quasi-cyclic (QC) low-density parity-check (LDPC) code, a full-length row-multiplier (FLRM) QC-LDPC code is described by a compact exponent matrix based on two sequences of integers.
Juhua Wang+3 more
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4-CYCLE FREE APM LDPC CODES WITH AN EXPLICIT CONSTRUCTION [PDF]
Recently, a class of low-density parity-check codes based on affine permutation matrices, called APM-LDPC codes, have been considered which have some advantages than quasi-cyclic (QC) LDPC codes in terms of minimum-distance, cycle distribution, and error-
Z. Gholami, M. Gholami
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Optimizing quasi-cyclic spatially coupled LDPC codes by eliminating harmful objects
It is well known that some harmful objects in the Tanner graph of low-density parity-check (LDPC) codes have a negative impact on their error correction performance under iterative message-passing decoding.
Massimo Battaglioni+4 more
doaj +1 more source
Area‐ and energy‐efficient high‐throughput QC‐LDPC encoder for space applications
An area‐ and energy‐efficient encoding method and encoder architecture are proposed using a bit selector before bit XOR operations in vector–matrix multiplication. A fully parallel low‐density parity check encoder is implemented on the aiwan Semiconductor Manufacturing Company (TSMC) 90 nm complementary metal oxide semiconductor (CMOS) technology ...
Lintao Li, Jiayi Lv, Yimin Li
wiley +1 more source
ON THE CLASS OF ARRAY-BASED APM-LDPC CODES [PDF]
We construct an explicit class of affine permutation matrix low-density parity-check (APM-LDPC) codes based on the array parity-check matrix by using two affine maps f (x) = x-1 and g(x) = 2x-1 on Z_m, where m is an odd prime number, with girth 6 and ...
A. Nassaj, A. R. Naghipour
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With the rapid development of 5G communication and wireless Internet of Things technology, the application of intelligent wearable devices based on wireless data transmission technology is becoming more and more popular. However, due to the bandwidth of wireless data transmission nodes and the power consumption of the device system, the use time and ...
Yaguang Yang+4 more
wiley +1 more source
Embedded Parallel Implementation of LDPC Decoder for Ultra‐Reliable Low‐Latency Communications
Ultra‐reliable low‐latency communications, URLLC, are designed for applications such as self‐driving cars and telesurgery requiring a response in milliseconds and are very sensitive to transmission errors. To match the computational complexity of LDPC decoding algorithms to URLLC applications on IoT devices having very limited computational resources ...
Mhammed Benhayoun+4 more
wiley +1 more source
Performance analysis of LDPC coded GFDM systems
Abstract This paper analyzes the error probability performance of low‐density parity‐check (LDPC) coded generalized frequency division multiplexing (GFDM) systems over Rayleigh fading and additive white Gaussian noise (AWGN) channels. The initial log‐likelihood ratio (LLR) expressions used in the sum‐product algorithm (SPA) decoder are first derived ...
Yanpeng Wang, Paul Fortier
wiley +1 more source