Results 51 to 60 of about 1,996 (184)
Coset‐based QC‐LDPC codes without small cycles
Electronics Letters, 2014 A simple and efficient search method based on the coset concept is proposed to construct (3, L ) quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes without small cycles. Compared with the random search method, the chance to find large‐girth codes is remarkably increased for the new method.
Juhua Wang, Guohua Zhang, Quan Zhou
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Quasi-Cyclic Asymptotically Regular LDPC Codes
, 2010 Families of "asymptotically regular" LDPC block code ensembles can be formed by terminating (J,K)-regular protograph-based LDPC convolutional codes. By varying the termination length, we obtain a large selection of LDPC block code ensembles with varying ...
Costello Jr, Daniel J. +3 more
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Explicit constructions of Type-II QC LDPC codes with girth at least 6 [PDF]
, 2007 Type-II quasi-cyclic (QC) LDPC codes are constructed from combinations of weight-0, weight-1 and weight-2 circulant matrices. The structure of cycles of length 2n are investigated, and necessary and sufficient conditions for a type-II QC LDPC parity ...
Lally, K
core
Floor Scale Modulo Lifting for QC-LDPC codes
, 2017 7 pages, 2 ...
Polyanskii, Nikita +2 more
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Type-II QC-LDPC Codes From Multiplicative Subgroup of Prime Field
IEEE Access, 2020 A quasi-cyclic (QC) low-density parity-check (LDPC) code is called type-II, if the maximum weight over all circulants appearing in the parity-check matrix has the value of two. On the basis of multiplicative subgroup analysis for the prime field, a novel
Guohua Zhang +4 more
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Novel construction of QC-LDPC codes with modified 2-D GRS codes
Tongxin xuebao, 2015 The construction method for QC-LDPC (quasi-cyclic low density parity-check) code with modified two-dimensional generalized reed-solomon (2-D GRS) code is proposed using the generator polynomial of GRS code,so thus the constructed code can have better ...
Ming ZHAO, Xiao-lin ZHANG
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Low Power QC-LDPC Decoder Based on Token Ring Architecture
Energies, 2020 The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption.
Mateusz Kuc +2 more
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Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders
, 2017 Polar codes are a recently proposed family of provably capacity-achieving error-correction codes that received a lot of attention. While their theoretical properties render them interesting, their practicality compared to other types of codes has not ...
Balatsoukas-Stimming, Alexios +2 more
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Rate‐compatible QC‐LDPC codes based on PEXIT [PDF]
Electronics Letters, 2018 An improved extension method based on protograph extrinsic information transfer (PEXIT) charts is proposed to design rate‐compatible quasi‐cyclic low‐density parity‐check (QC‐LDPC) codes with more flexible rates and better performance. The masking matrix of the highest‐rate code can first be constructed column by column to own the lowest decoding ...
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Multisource SWIPT-based coded cooperation:rate compatible codes and codeword splitting protocol
EURASIP Journal on Wireless Communications and Networking, 2020 To achieve a high reliable and energy-saving green communication, we investigate a multisource simultaneous wireless information and power transfer (SWIPT)-based coded cooperation where the relay can realize information decoding and energy harvesting ...
Shunwai Zhang, Lingjun Kong, Jun Li
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