Efficient Unified Arithmetic for Hardware Cryptography [PDF]
, 2008 The basic arithmetic operations (i.e. addition, multiplication, and inversion) in finite fields, GF(q), where q = pk and p is a prime integer, have several applications in cryptography, such as RSA algorithm, Diffie-Hellman key exchange algorithm [1 ...
Koc, Cetin Kaya +3 more
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A versatile Montgomery multiplier architecture with characteristic three support [PDF]
, 2008 We present a novel unified core design which is extended to realize Montgomery multiplication in the fields GF(2n), GF(3m), and GF(p). Our unified design supports RSA and elliptic curve schemes, as well as the identity-based encryption which requires a ...
Ozturk, Erdinc +4 more
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Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP [PDF]
, 2009 Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class
Hauck, S.A. +3 more
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Bit-level pipelined digit-serial array processors [PDF]
, 1998 A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n ...
Aggoun, A, Ashur, A, Ibrahim, MK
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A study of the communication cost of the FFT on torus multicomputers [PDF]
, 1995 The computation of a one-dimensional FFT on a c-dimensional torus multicomputer is analyzed. Different approaches are proposed which differ in the way they use the interconnection network. The first approach is based on the multidimensional index mapping
Díaz de Cerio Ripalda, Luis Manuel +2 more
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A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM
, 2004 In this article, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in the OFDM based IEEE 802.11a Wireless LAN (WLAN) baseband processor.
Grass, Eckhard +2 more
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Optimal Networks from Error Correcting Codes
, 2013 To address growth challenges facing large Data Centers and supercomputing clusters a new construction is presented for scalable, high throughput, low latency networks.
Tomic, Ratko V.
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Chain Reduction for Binary and Zero-Suppressed Decision Diagrams
, 2017 Chain reduction enables reduced ordered binary decision diagrams (BDDs) and zero-suppressed binary decision diagrams (ZDDs) to each take advantage of the others' ability to symbolically represent Boolean functions in compact form.
Bryant +5 more
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Towards hardware acceleration of neuroevolution for multimedia processing applications on mobile devices [PDF]
, 2006 This paper addresses the problem of accelerating large artificial neural networks (ANN), whose topology and weights can evolve via the use of a genetic algorithm.
A.R. Omondi +10 more
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Rational series and asymptotic expansion for linear homogeneous divide-and-conquer recurrences [PDF]
, 2013 Among all sequences that satisfy a divide-and-conquer recurrence, the sequences that are rational with respect to a numeration system are certainly the most immediate and most essential.
Dumas, Philippe
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