Results 251 to 260 of about 170,253 (289)

Trends in reconfigurable logic and reconfigurable computing

9th International Conference on Electronics, Circuits and Systems, 2003
The paper gives a survey on reconfigurable logic and reconfigurable computing technologies, and on recent R&D trends in these areas. The paper also points out the weaker aspects of recent developments and proposes new directions to follow, driven by technology progress, a growing variety of reconfigurable platforms, and, innovations in EDA.
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A reconfigurable future

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798), 2004
There are a plethora of new emerging system applications for reconfigurable architectures. Interest in reconfigurability is steadily increasing and reconfigurability has evolved from basic programmable structures to include advanced architectural components including processors, DSP blocks and connectivity.
Phil Bishop, Chris Sullivan
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A reconfigurable unit for a clustered programmable-reconfigurable processor

Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays, 2004
In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam ...
Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter   +4 more
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Synthesis of efficiently reconfigurable datapaths for reconfigurable computing

2008 International Conference on Field-Programmable Technology, 2008
We present new approach to optimize circuits for dynamic reconfiguration in FPGAs. Within a high level synthesis tool we optimize the binding of operations to resources to achieve high re-use of resources and interconnect between different configurations.
Markus Rullmann, Renate Merker
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Analysis of Reconfiguration Options for a Reconfigurable Polymorphic Circuit

2008 NASA/ESA Conference on Adaptive Hardware and Systems, 2008
REconfigurable POlymorphic MOdule (REPOMO) will be a new reconfigurable chip intended for experimental applications of evolvable and polymorphic hardware. In this paper, we analyze various reconfiguration options for this platform with the aim of finding such a reconfiguration subsystem which maximizes the success rate of evolutionary circuit design ...
Zdenek Vasícek, Ladislav Capka, Lukás Sekanina   +2 more
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Array partitioning: a methodology for reconfigurability and reconfiguration problems

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
An approach to array fault tolerance is presented. A parametric tool for reconfigurability detection and reconfiguration of arrays is introduced. The underlying methodology is based on a partitioning algorithm to determine reconfigurability. After reconfiguration a compaction algorithm is used to optimize results. The application of this methodology to
DISTANTE, FAUSTO, LOMBARDI F., SCIUTO, DONATELLA   +2 more
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Design for reconfiguration

Proceedings of the 26th annual ACM international conference on Design of communication, 2008
The desktop computer has been part of our work-life for a while. Even so many work situations do not consist solely of work at the desktop. Many other artefacts are used in changing configurations with and around the computer. Most user interface design has failed to recognize this, and accordingly we are still stuck with the idea that new design ...
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Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures

Circuits, Systems, and Signal Processing, 2017
Dynamically reconfigurable architectures, such as NATURE, achieve high logic density and low reconfiguration latency compared to traditional field-programmable gate arrays. Unlike fine-grained NATURE, reconfigurable DSP block incorporated NATURE architecture achieves significant improvement in performance for mapping compute-intensive arithmetic ...
Warrier, Rakesh, Zhang, Wei, Vun, Chan Hua   +2 more
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Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices

IEEE Design and Test of Computers, 2005
This article presents two approaches to solving the problem of communication between components dynamically placed at runtime on a reconfigurable device. The first is a circuit-routing approach designed for existing FPGAs. This approach uses the reconfigurable multiple bus (RMB).
Christophe Bobda, Ali Ahmadinia
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A scalable reconfiguration mechanism for fast dynamic reconfiguration

2008 International Conference on Field-Programmable Technology, 2008
Hardware reconfiguration during run-time provides attractive features like fast adaptivity, high hardware utilisation, and low area consumption due to efficient reuse of hardware components. In this paper, a novel multi-layered reconfiguration mechanism is proposed that allows frequent dynamic reconfiguration at very low latencies.
Heiko Hinkelmann, Peter Zipf, Manfred Glesner   +2 more
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