Results 181 to 190 of about 60,987 (263)
Reliable Computing with Ultra-Reduced Instruction Set Coprocessors
IEEE Micro, 2014 This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete instruction can mirror any other instruction's semantics.
Dan Wang +5 more
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HewlettâPackard precision architecture: A practical example of reduced instruction set computing
The Physics Teacher, 1987 James T. Hunt
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Reduced Instruction Set Computing
Wiley Encyclopedia of Computer Science and Engineering, 2007 Reduced instruction set computing (RISC) architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level.
Vojin G. Oklobdzija
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Complex versus reduced instruction set computers
1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and ...
David A. Patterson, S. Seccombe
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Built-in self test and a VLSI stack-frame reduced-instruction set computer (RISC) architecture
IEEE Conference on Aerospace and Electronics, 2002The authors describe the construction of the SF2000 VLSI stack-frame RISC computer (a design based on the successful SF1 computer) and discuss the advanced methods, such as random pattern testing and design partitioning aids, used in the construction of the on-chip BIST (built-in self test) hardware in this three-chip computer. The SF2000 CPU chip will
R. Siferd +4 more
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High Performance Data Level Parallelism based Instruction Set Architecture in RISC-V
Conference Information and Communication Technology, 2023Performance is an indispensable factor in processes related to computer architecture. Data Level Parallelism (DLP) is useful to operate on multiple data streams under a single instruction multiple data (SIMD) instructions for improving the performance of
C. Sri, G. J. Israel, Mohamed Asan
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The case for the reduced instruction set computer [PDF]
ACM SIGARCH Computer Architecture News, 1980 One of the primary goals of computer architects is to design computers that are more costeffective than their predecessors. Cost-effectiveness includes the cost of hardware to manufacture the machine, the cost of programming, and costs incurred related to the architecture in debugging both the initial hardware and subsequent programs.
David R. Ditzel, David A. Patterson
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Design of computing granularity configurable processor based on RISC-V extended instruction
IEEE International Conference on Solid-State and Integrated Circuit Technology, 2022Aiming at the problems of long operation time and poor flexibility of embedded processor, this paper proposes a structure of configurable execution unit based on RISC-V extended instruction set for computing granularity.
Bin He, N. Yu, Meng Xu, Xing Wang
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Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer
IEEE Micro, 1987GaAs now allows up to 30K transistors per chip. With such a limitation, can you build a 32-bit CISC on a single GaAs chip? Yes, if you build a reduced instruction set computer and emulate the 32-bit CISC on it.
Veljko Milutinovic, Kevin John McNeley
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Reduced Instruction Set Computer Design on FPGA
2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA, 2021The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. The basic modules of this processor are programmed and simulated using Verilog HDL (Hardware Description Language), and implemented on Cyclone IV FPGA (Field Programmable Gate Arrays)
Mohamed M. Eljhani, Veton Kepuska
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