Results 201 to 210 of about 179,330 (266)
Reliable computing with ultra-reduced instruction set co-processors
This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete instruction can mirror any other instruction's semantics.
Aravindkumar Rajendiran +4 more
+4 more sources
Some of the next articles are maybe not open access.
Related searches:
Related searches:
Reduced instruction set computers
Communications of the ACM, 1985Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.
openaire +3 more sources
Reliable Computing with Ultra-Reduced Instruction Set Coprocessors
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instruction can mirror the semantics of any other instruction.
Dan Wang +5 more
openalex +2 more sources
Reduced instruction set computer architecture
Proceedings of the IEEE, 1988A tutorial on the reduced instruction set computer (RISC) approach is presented and the key design issues involved in RISC architecture are highlighted. The results of a number of studies on the instruction execution characteristics of compiled high-level-language programs are examined first.
openaire +3 more sources
Complex versus reduced instruction set computers
1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and ...
D. Patterson, S. Seccombe
openaire +3 more sources

