Analysis on the Possibility of RISC-V Adoption [PDF]
, 2020 As the interface between hardware and software, Instruction Set Architectures (ISAs) play a key role in the operation of computers. While both hardware and software have continued to evolve rapidly over time, ISAs have undergone minimal change. Since its
Scott, Ian
core
Low-complexity distributed issue queue [PDF]
, 2004 As technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the processor performance. We present a
Abella Ferrer, Jaume +1 more
core +1 more source
The "MIND" Scalable PIM Architecture [PDF]
, 2005 MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing.
Brodowicz, Maciej, Sterling, Thomas
core +1 more source
A system on chip-based real-time tracking system for amphibious spherical robots
International Journal of Advanced Robotic Systems, 2017 Aiming at vision applications of our amphibious spherical robot, a real-time detection and tracking system adopting Gaussian background model and compressive tracking algorithm was designed and implemented in this article.
Shuxiang Guo +6 more
doaj +1 more source
Application of regional meteorology and air quality models based on the microprocessor without interlocked piped stages (MIPS) and LoongArch CPU platforms [PDF]
Geoscientific Model DevelopmentThe microprocessor without interlocked piped stages (MIPS) and LoongArch are reduced instruction set computing (RISC) processor architectures, which have advantages in terms of energy consumption and efficiency.
Z. Bai +8 more
doaj +1 more source
Reproducibility, accuracy and performance of the Feltor code and library on parallel computer architectures [PDF]
, 2018 Feltor is a modular and free scientific software package. It allows developing platform independent code that runs on a variety of parallel computer architectures ranging from laptop CPUs to multi-GPU distributed memory systems. Feltor consists of both a
Einkemmer, Lukas +5 more
core +2 more sources
Instruction Set Architectures for Quantum Processing Units
, 2017 Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows.
AR Calderbank +3 more
core +1 more source
Evaluating kernels on Xeon Phi to accelerate Gysela application [PDF]
, 2014 This work describes the challenges presented by porting parts ofthe Gysela code to the Intel Xeon Phi coprocessor, as well as techniques used for optimization, vectorization and tuning that can be applied to other applications.
Bigot, J. +5 more
core +4 more sources
PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP [PDF]
ICTACT Journal on Soft Computing, 2012 In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time.
R. Maheswari, V. Pattabiraman
doaj
On Hardware Flexibility and Heterogeneity: A Vision for Monte Carlo Codes on Incoming RISC-V Computing Devices with AI-based Cross Section [PDF]
EPJ Web of ConferencesAs an open-sourced instruction set and being flexible in hardware extension, RISC-V begins its pace to enter the world of high performance computing.
Liu Changyuan
doaj +1 more source