Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review [PDF]
, 2009 The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range.
Gujarathi, Hemal S +2 more
core +2 more sources
Instruction Set Architectures for Quantum Processing Units
, 2017 Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows.
AR Calderbank +3 more
core +1 more source
A system on chip-based real-time tracking system for amphibious spherical robots
International Journal of Advanced Robotic Systems, 2017 Aiming at vision applications of our amphibious spherical robot, a real-time detection and tracking system adopting Gaussian background model and compressive tracking algorithm was designed and implemented in this article.
Shuxiang Guo +6 more
doaj +1 more source
Application of regional meteorology and air quality models based on the microprocessor without interlocked piped stages (MIPS) and LoongArch CPU platforms [PDF]
Geoscientific Model DevelopmentThe microprocessor without interlocked piped stages (MIPS) and LoongArch are reduced instruction set computing (RISC) processor architectures, which have advantages in terms of energy consumption and efficiency.
Z. Bai +8 more
doaj +1 more source
Research and Implementation of Performance Optimization Methods for RISC-V Level-5 Processors
Applied SciencesThe widespread adoption of fifth-generation Reduced Instruction Set Computing (RISC-V) processors in embedded systems has driven advancements in domestic processor design.
Zhiwei Jin +3 more
doaj +1 more source
PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP [PDF]
ICTACT Journal on Soft Computing, 2012 In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time.
R. Maheswari, V. Pattabiraman
doaj
Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP [PDF]
, 2009 Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class
Hauck, S.A. +3 more
core +7 more sources
On Hardware Flexibility and Heterogeneity: A Vision for Monte Carlo Codes on Incoming RISC-V Computing Devices with AI-based Cross Section [PDF]
EPJ Web of ConferencesAs an open-sourced instruction set and being flexible in hardware extension, RISC-V begins its pace to enter the world of high performance computing.
Liu Changyuan
doaj +1 more source
Optimizing Quantum Programs against Decoherence: Delaying Qubits into Quantum Superposition
, 2019 Quantum computing technology has reached a second renaissance in the last decade. However, in the NISQ era pointed out by John Preskill in 2018, quantum noise and decoherence, which affect the accuracy and execution effect of quantum programs, cannot be ...
Deng, Haowei +4 more
core +1 more source
On-Line Instruction-checking in Pipelined Microprocessors [PDF]
, 2008 Microprocessors performances have increased by more than five orders of magnitude in the last three decades. As technology scales down, these components become inherently unreliable posing major design and test challenges.
Di Carlo, Stefano +2 more
core +3 more sources