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Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

IEEE Journal of Solid-State Circuits, 2014
The design of resistive RAM (ReRAM) faces two major challenges: 1) cell area versus write current requirements and 2) cell read current (ICELL) versus read disturbance. This paper proposes ReRAM macros using logic-process-based vertical parasitic-BJT (VPBJT) switches and a corresponding cell array (VPBJT-CA), resulting in a 4.5× macro density compared ...
Meng-Fan Chang   +9 more
openaire   +2 more sources

A sub-0.5V charge pump circuit for resistive RAM (ReRAM) enabled low supply voltage nonvolatile logics and nonvoaltile processors

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2016
Meng-Fan Chang   +8 more
openaire   +2 more sources

Synaptic Emulated by Double-Layer ZnO Resistive RAM (ReRAM) via Optimized Sputter and Low-Temperature ALD Process

2025 Silicon Nanoelectronics Workshop (SNW)
To realize a synaptic device supporting multi-mode modulation by optical and electrical signals, we systematically studied the optoelectronic properties of the ZnO ReRAM devices in single-layer Cu/ZnO(ALD)/ZnO(MS)/Si structure fabricated via magnetron ...
Junyao Mei   +9 more
openaire   +2 more sources

Experimental Study on Double-Layer ZnO Resistive RAM (ReRAM) by Co-Optimized Sputtering and Low-Temperature ALD Processes

2025 Silicon Nanoelectronics Workshop (SNW)
This work proposed a double-layer ZnO resistive random-access-memory (ReRAM) by magnetron sputtering (MS) and low temperature (70°C) atomic layer deposition (ALD).
Junyao Mei   +9 more
openaire   +2 more sources

Resistive RAM-based PUF: Challenges and Opportunities

2023 IEEE 16th Dallas Circuits and Systems Conference (DCAS), 2023
The demand for electronic device authentication is growing sky-high due to the widespread use of IoT devices. An effective method for hardware-level device authentication is CMOS-based Physically Unclonable Function (PUF).
Mojahidul Ahsan   +3 more
semanticscholar   +1 more source

Controllable Conductive Filament Formation in Resistive-RAM Using ZnO Nanoparticles and Its Mechanisms

IEEE Electron Devices Technology and Manufacturing Conference, 2023
In this study, ZnO nanoparticles (NPs) are suggested to improve the uniformity in ReRAM by reducing the formation energy of oxygen vacancy. Electrical measurement and density functional theory calculation (DFT) are performed to confirm the role of ZnO ...
Jun-Ho Byun   +7 more
semanticscholar   +1 more source

Structural and Electrical Properties of Pure and Samarium Doped MgFe2O4 Nanoparticles for Resistive RAM Applications

Nano Hybrids and Composites, 2022
Spinel ferrites nanoparticles have attracted the attention of researcher for memory storage devices. We have synthesized MgFeO4 pure sample and MgFe1.8Sm0.2O4 doped sample via solgel technique.
Haroon Mazhar, M. Anis-Ur-Rehman
semanticscholar   +1 more source

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)

2011 9th IEEE International Conference on ASIC, 2011
Low power 3D-IC is well-suited to mobile systems; however, it poses a number of challenges associated with thermal stress, particularly in designs with many stacked layers. The use of a low supply voltage (VDD) and power-down mode help to reduce the power consumption of 3D-ICs, while alleviating aging and thermal effects.
Meng-Fan Chang   +4 more
openaire   +1 more source

Multifunctionality in ferromagnetic shape memory alloy-based resistive switching memory for flexible ReRAM application

Applied Physics Letters, 2022
Multifunctional flexible electronics is the ongoing demand for fabricating wearable data storage and communication devices. The magnetoelectric (ME) heterostructure consisting of piezoelectric (AlN) and ferromagnetic magnetic shape memory alloy [FSMA (Ni–
Pradeep Kumar, D. Kaur
semanticscholar   +1 more source

Nanoscale filaments in Ta-O resistive RAM bit array: microscopy analysis and switching property

International Memory Workshop, 2019
Ta-O-based resistive random access memory (ReRAM) cells arranged in one-transistor-one-resistor (1T1R) bit arrays were investigated using scanning transmission electron microscopy (STEM) in combination with energy dispersive X-ray spectroscopy (EDS ...
M. Arita   +5 more
semanticscholar   +1 more source

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