Results 81 to 90 of about 4,276 (120)

Hardware implementation of memristor-based artificial neural networks. [PDF]

Nat Commun
Aguirre F, Sebastian A, Le Gallo M, Song W, Wang T, Yang JJ, Lu W, Chang MF, Ielmini D, Yang Y, Mehonic A, Kenyon A, Villena MA, Roldán JB, Wu Y, Hsu HH, Raghavan N, Suñé J, Miranda E, Eltawil A, Setti G, Smagulova K, Salama KN, Krestinskaya O, Yan X, Ang KW, Jain S, Li S, Alharbi O, Pazos S, Lanza M.   +30 more
europepmc   +1 more source

Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysis. [PDF]

PLoS One
S HR, Nelapati RP.
europepmc   +1 more source

Integrated Circuits on Fiber Substrates: State-of-the-Art System-on-Fiber Technologies for Smart Textiles and Wearables. [PDF]

Nanomicro Lett
Jin J, Won J, Kim D, Arumugasamy SK, Park S, Kim TW.   +5 more
europepmc   +1 more source

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Ion Beam Etch for Patterning of Resistive RAM (ReRAM) Devices

MRS Advances, 2017
We investigate the feasibility of inert ion beam etch (IBE) for subtractive patterning of ReRAM-type structures. We report on the role of the angle-dependent ion beam etch rates in device area control and the minimization of sidewall re-deposition. The etch rates of key ReRAM materials are presented versus incidence angle and ion beam energy.
Narasimhan Srinivasan, Katrina Rook, Ivan Berry, Binyamin Rubin, Frank Cerio   +4 more
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A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

IEEE Journal of Solid-State Circuits, 2013
ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance.
Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai   +14 more
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A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

2012 IEEE International Solid-State Circuits Conference, 2012
Numerous low-supply-voltage (V DD ) mobile chips, such as energy-harvesting-powered devices and biomedical applications, require low-V DD on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs cannot achieve low-V DD operation due to insufficient write voltage generated by charge ...
Meng-Fan Chang, Che-Wei Wu, Chia-Cheng Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih   +8 more
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A low-power subthreshold-to-superthreshold level-shifter for sub-0.5V embedded resistive RAM (ReRAM) macro in ultra low-voltage chips

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014
Many mobile chips with low supply voltage (VDD) require low-voltage embedded nonvolatile memory (eNVM) to enable low-power read operations and zero-standby-current power-off storage. ReRAM has a lower write-voltage (V W ), smaller write-current (I w ), and larger resistance-ratio than other NVMs, making it a good candidate for low-VDD eNVM, as long as ...
Meng-Fan Chang, Che-Wei Wu, Jui-Yu Hung, Ya-Chin King, Chomg-Jung Lin, Mon-Shu Ho, Chia-Cheng Kuo, Shyh-Shyuan Sheu   +7 more
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A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro

IEEE Journal of Solid-State Circuits, 2013
ReRAM is a promising candidate for on-chip low-VDD NVM due to its superior write behavior, particularly for frequent-read-seldom-write applications. Nonetheless, this approach requires a robust and fast low-VDD read scheme. Current-mode sense amplifiers (CSA) are commonly used in NVM; however, they suffer low-yield and degraded speed at a low VDD, due ...
null Meng-Fan Chang, null Che-Wei Wu, null Chia-Cheng Kuo, null Shin-Jang Shen, null Sue-Meng Yang, null Ku-Feng Lin, null Wen-Chao Shen, null Ya-Chin King, null Chorng-Jung Lin, null Yu-Der Chih   +9 more
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Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections

2009 14th IEEE European Test Symposium, 2009
Emerging concepts of non-volatile memories are more and more investigated to replace conventional charge storage-based devices like EEPROM or Flash. One of these promising memory concepts is called Resistive Switching Memory (ReRAM). Such memory is based on a switching mechanism controlled in current and/or voltage, between two distinct resistive ...
O. Ginez, J.-M. Portal, Ch. Muller
openaire   +2 more sources