Results 211 to 220 of about 35,633 (259)

An ECL RISC multiprocessor

COMPCON Spring '91 Digest of Papers, 2002
The authors describe how an upgrade to the MIPS R6000 ECL chip set, the R6000A CPU and the R6020A SBC, implements a sophisticated coherent cache protocol to support multiple processor systems, and how software uses the system. Particular attention is given to the cache subsystem, the cache control attributes, the cache line states, and the software ...
Bob Foster, Curtis Alexander, Allen Roberts, David Roberts   +3 more
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Are operating systems at RISC?

2005
A new generation of high speed microprocessors has become the standard in a number of workstation environments. The technology, RISC, has made high speed processing a reality at a relatively low price. The basic design goal of the RISC is aimed at higher speed execution of application programs and was based on an analysis of volumes of such code. It is
Arthur I. Karshmer, James N. Thomas
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RISC-V²: A Scalable RISC-V Vector Processor

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020
Machine learning adoption has seen a widespread bloom in recent years, with neural network implementations being at the forefront. In light of these developments, vector processors are currently experiencing a resurgence of interest, due to their inherent amenability to accelerate data-parallel algorithms required in machine learning environments.
Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos   +3 more
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SUNNY-RISC: a VLSI RISC micro-architecture

IEEE Technical Conference on Southern Tier, 2002
A VLSI reduced instruction set computer (RISC) microarchitecture called SUNY-RISC is described. The SUNY-RISC processor is a 16-bit microarchitecture. Most of the instructions are register to register. This approach results in fast execution and simple control logic. SUNY-RISC has some similarities with RISC approaches; however, this machine introduces
I. Chen, J. Goshtasbi, S. Hsu, M. Strauss, T. Wang, J.G. Delgado-Frias   +5 more
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The RISC BLAS

ACM Transactions on Mathematical Software, 1999
We describe a version of the Level 3 BLAS which is designed to be efficient on RISC processors. This is an extension of previous studies by the authors and colleagues on a similar approach for efficient serial and parallel implementations on virtual-memory and shared-memory multiprocessors.
Daydé, Michel, Duff, Iain
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A fuzzy RISC processor

IEEE Transactions on Fuzzy Systems, 2000
We describe application-specific extensions for fuzzy processing to a general purpose processor. The application-specific instruction set extensions were defined and evaluated using hardware/software codesign techniques. Based on this approach, we have extended the MIPS instruction set architecture with only a few new instructions to significantly ...
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Beyond RISC - The Post-RISC Architecture

1996
The principles of the RISC architecture guided the design of the previous generation of processors. These principles have accelerated the performance gains of these processors over their predecessors. The current generation of CPUs is poised to continue this rapid acceleration of performance.
Brehob, Mark, Doom, Travis E., Enbody, Richard, Moore, William H., Moore, Sherry Q., Sass, Ron, Severance, Charles   +6 more
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A novel 32 bit RISC architecture unifying RISC and DSP

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002
A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit fixed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed.
Christoph Baumhof, Frank Müller, Otto Müller, Manfred Schlett   +3 more
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RISC architecture of the M88000

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
The 88000 processor family is one of the RISC (reduced-instruction-set computer) microcomputers that integrate the integer execution unit, the floating-point unit, the instruction fetch pipelines, and a data memory unit interface onto a single device.
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Compiler challenges with RISCs

IEEE Micro, 1990
It is argued that despite the simplified instruction sets of reduced instruction-set computers (RISCs), designing their compilers is not so simple. This viewpoint is substantiated by considering a subproblem that arises in designing a calling sequence, namely, how to pass arguments to a procedure.
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