Results 251 to 260 of about 81,703 (295)

A comparison of RISC architectures

IEEE Micro, 1989
Three new RISC (reduced instruction set computer) architectures, the Intel i860, the Motorola 88000, and the Sun Microsystems Sparc, are compared. The relative importance of an architectural comparison, as opposed to a comparison of implementations, is discussed, followed by a high-level overview of each of the architectures. The relative strengths and
Richard S. Piepho, William S. Wu
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Are operating systems at RISC?

2005
A new generation of high speed microprocessors has become the standard in a number of workstation environments. The technology, RISC, has made high speed processing a reality at a relatively low price. The basic design goal of the RISC is aimed at higher speed execution of application programs and was based on an analysis of volumes of such code. It is
Arthur I. Karshmer, James N. Thomas
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RISC-V²: A Scalable RISC-V Vector Processor

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020
Machine learning adoption has seen a widespread bloom in recent years, with neural network implementations being at the forefront. In light of these developments, vector processors are currently experiencing a resurgence of interest, due to their inherent amenability to accelerate data-parallel algorithms required in machine learning environments.
Karyofyllis Patsidis, Chrysostomos Nicopoulos, Georgios Ch. Sirakoulis, Giorgos Dimitrakopoulos   +3 more
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Compiler challenges with RISCs

IEEE Micro, 1990
It is argued that despite the simplified instruction sets of reduced instruction-set computers (RISCs), designing their compilers is not so simple. This viewpoint is substantiated by considering a subproblem that arises in designing a calling sequence, namely, how to pass arguments to a procedure.
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SUNNY-RISC: a VLSI RISC micro-architecture

IEEE Technical Conference on Southern Tier, 2002
A VLSI reduced instruction set computer (RISC) microarchitecture called SUNY-RISC is described. The SUNY-RISC processor is a 16-bit microarchitecture. Most of the instructions are register to register. This approach results in fast execution and simple control logic. SUNY-RISC has some similarities with RISC approaches; however, this machine introduces
I. Chen, J. Goshtasbi, S. Hsu, M. Strauss, T. Wang, J.G. Delgado-Frias   +5 more
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A novel 32 bit RISC architecture unifying RISC and DSP

1997 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2002
A novel 32 bit RISC architecture is presented which is the basis of a powerful general purpose microprocessor and in parallel a 16/32 bit fixed point DSP processor. This unifying of RISC and DSP was not achieved by simply using a microprocessor and DSP core, but a new concept for the implementation of DSP processors has been developed.
Christoph Baumhof, Frank Müller, Otto Müller, Manfred Schlett   +3 more
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A fuzzy RISC processor

IEEE Transactions on Fuzzy Systems, 2000
We describe application-specific extensions for fuzzy processing to a general purpose processor. The application-specific instruction set extensions were defined and evaluated using hardware/software codesign techniques. Based on this approach, we have extended the MIPS instruction set architecture with only a few new instructions to significantly ...
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The evolution of RISC technology at IBM

IBM Journal of Research and Development, 1990
This paper traces the evolution of IBM RISC architecture from its origins in the 1970s at the IBM Thomas J. Watson Research Center to the present-day IBM RISC System/6000* computer. The acronym RISC, for Reduced Instruction-Set Computer, is used in this paper to describe the 801 and subsequent architectures.
John Cocke, Victoria Markstein
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RISC architecture of the M88000

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
The 88000 processor family is one of the RISC (reduced-instruction-set computer) microcomputers that integrate the integer execution unit, the floating-point unit, the instruction fetch pipelines, and a data memory unit interface onto a single device.
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An implementation of the BLAS on the i860: A RISC approach to software for RISC devices

1992
The Liverpool Single-transputer library [10] was ported to the i860 as part of the Esprit Genesis project, P2702. There are approximately 250 routines in this library, including the BLAS (which are a well-known set of subroutines providing functions commonly used in numerical computing, see [8],[3], [2],[1]) and a set of vector routines, known as the ...
Bob Wilkinson, Lawrence S. Mulholland
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