Results 241 to 250 of about 81,703 (295)
Some of the next articles are maybe not open access.
ACM SIGMICRO Newsletter, 1986
A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using
David K. DuBose +2 more
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A new, microcoded, RISC-type system is proposed and presented. The microcode is stored in a 256 x 64 PROM Nanomemory in the CPU. The 8-bit opcode of each instruction is a direct address to the Nanomemory. Each Nanomemory 64-bit word (horizontal microcode) corresponds to a specific machine language instruction. A large 2048 x 32 CPU Register file, using
David K. DuBose +2 more
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Trends in Biochemical Sciences, 2010
It is well established that 20- to 30-nt small RNAs, including small interfering RNAs, microRNAs and Piwi-interacting RNAs, play crucial roles in regulating gene expression and control a surprisingly diverse array of biological processes. These small RNAs cannot work alone: they must form effector ribonucleoprotein complexes - RNA-induced silencing ...
Tomoko Kawamata, Tomari, Yukihide
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It is well established that 20- to 30-nt small RNAs, including small interfering RNAs, microRNAs and Piwi-interacting RNAs, play crucial roles in regulating gene expression and control a surprisingly diverse array of biological processes. These small RNAs cannot work alone: they must form effector ribonucleoprotein complexes - RNA-induced silencing ...
Tomoko Kawamata, Tomari, Yukihide
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Communications of the ACM, 2018
ACM A.M. Turing Award recipients David Patterson and John Hennessy developed the "dangerous" idea that software should be simpler so it can be executed more quickly, which evolved into the Reduced Instruction Set Computer architecture.
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ACM A.M. Turing Award recipients David Patterson and John Hennessy developed the "dangerous" idea that software should be simpler so it can be executed more quickly, which evolved into the Reduced Instruction Set Computer architecture.
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ACM SIGARCH Computer Architecture News, 1988
Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.
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Reduced instruction set computer (RISC) architectures have attracted considerable interest during the past decade. The ultimate RISC architecture presented here is an extreme yet simple illustration of such an architecture. It has only one instruction, move memory to memory, yet it is useful.
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Communications of the ACM, 2018
ACM A.M. Turing award recipients John Hennessy and David Patterson have introduced generations of students to reduced instruction set computing.
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ACM A.M. Turing award recipients John Hennessy and David Patterson have introduced generations of students to reduced instruction set computing.
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IEEE Micro, 1995
All the major players in the workstation and personal computer market are committed to RISC. The author looks at the view that RISC is not better, and does not hold the key to high speed computing. He claims that the only reason this foolishness has got so far is that the real differences between RISC and complex-instruction-set computing (CISC) are ...
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All the major players in the workstation and personal computer market are committed to RISC. The author looks at the view that RISC is not better, and does not hold the key to high speed computing. He claims that the only reason this foolishness has got so far is that the real differences between RISC and complex-instruction-set computing (CISC) are ...
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A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs
2023 IEEE Symposium on Security and Privacy (SP), 2023Microarchitectural attacks threaten the security of computer systems even in the absence of software vulnerabilities. Such attacks are well explored on x86 and ARM CPUs, with a wide range of proposed but not-yet deployed hardware countermeasures. With the standardization of the RISC-V instruction set architecture and the announcement of support for the
Lukas Gerlach 0001 +3 more
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ACM Transactions on Mathematical Software, 1999
We describe a version of the Level 3 BLAS which is designed to be efficient on RISC processors. This is an extension of previous studies by the authors and colleagues on a similar approach for efficient serial and parallel implementations on virtual-memory and shared-memory multiprocessors.
Daydé, Michel, Duff, Iain
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We describe a version of the Level 3 BLAS which is designed to be efficient on RISC processors. This is an extension of previous studies by the authors and colleagues on a similar approach for efficient serial and parallel implementations on virtual-memory and shared-memory multiprocessors.
Daydé, Michel, Duff, Iain
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COMPCON Spring '91 Digest of Papers, 2002
The authors describe how an upgrade to the MIPS R6000 ECL chip set, the R6000A CPU and the R6020A SBC, implements a sophisticated coherent cache protocol to support multiple processor systems, and how software uses the system. Particular attention is given to the cache subsystem, the cache control attributes, the cache line states, and the software ...
Bob Foster +3 more
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The authors describe how an upgrade to the MIPS R6000 ECL chip set, the R6000A CPU and the R6020A SBC, implements a sophisticated coherent cache protocol to support multiple processor systems, and how software uses the system. Particular attention is given to the cache subsystem, the cache control attributes, the cache line states, and the software ...
Bob Foster +3 more
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IEEE Robotics & Automation Magazine, 1994
This article describes a framework that combines simple hardware traditionally used in manufacturing with sensor-based planning and design algorithms from robotics. For repetitive assembly, the authors argue that this combination can reduce start-up and maintenance costs, increase throughput, and greatly reduce the set-up and changeover times for new ...
John F. Canny, Ken Goldberg
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This article describes a framework that combines simple hardware traditionally used in manufacturing with sensor-based planning and design algorithms from robotics. For repetitive assembly, the authors argue that this combination can reduce start-up and maintenance costs, increase throughput, and greatly reduce the set-up and changeover times for new ...
John F. Canny, Ken Goldberg
openaire +1 more source