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A comparative analysis of traditional and AI-based routing algorithms in electronic design automation [PDF]

open access: closedApplied and Computational Engineering, 2023
Rapid advances in artificial intelligence (AI) and machine learning have had a significant impact on various fields, including electronic design automation (EDA). This study aims to compare current EDA routing algorithms with AI-based routing algorithms, highlighting their respective advantages and limitations.
Zheyi Shen
openalex   +2 more sources

Photonics design tool for advanced CMOS nodes [PDF]

open access: yesIET Optoelectronics, 9(4), 163 (2015), 2015
Recently, the authors have demonstrated large-scale integrated systems with several million transistors and hundreds of photonic elements. Yielding such large-scale integrated systems requires a design-for-manufacture rigour that is embodied in the 10 000 to 50 000 design rules that these designs must comply within advanced complementary metal-oxide ...
Alloatti, Luca   +4 more
arxiv   +3 more sources

Optimization of Branch Pipe Routing Considering Tee Constraint Ant Lion

open access: yesIEEE Access, 2023
Considering the complex nature of branch pipes, which typically exhibit one-to-many characteristics, a transformation is implemented to facilitate one-to-one pipe routing.
Haicheng Shen, Shiyu Liu
doaj   +1 more source

Interactive Visualization of the Printed Circuits Tracing Algorithms for Educational Purposes

open access: yesЦифровая трансформация, 2023
A software module that allows interactive demonstration of maze routing algorithms for tracing printed conductors, which, during their operation, use a grid representation of a discrete working space of a printed circuit board has been developed.
D. O. Petrov
doaj   +1 more source

Monolithic 3D Semiconductor Footprint Scaling Exploration Based on VFET Standard Cell Layout Methodology, Design Flow, and EDA Platform

open access: yesIEEE Access, 2022
Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we
Chung-Kuan Cheng   +3 more
doaj   +1 more source

Fog computing, applications , security and challenges, review [PDF]

open access: yes, 2018
The internet of things originates a world where on daily basis objects can join the internet and interchange information and in addition process, store, gather them from the nearby environment, and effectively mediate on it.
Chai, Chuah Wen, Rahman, Gohar
core   +2 more sources

A Hybrid Josephson Transmission Line and Passive Transmission Line Routing Framework for Single Flux Quantum Logic [PDF]

open access: yes, 2022
The Single Flux Quantum (SFQ) logic family is a novel digital logic as it provides ultra-fast and energy-efficient circuits. For large-scale SFQ circuit design, specialized electronic design automation (EDA) tools are required due to the differences in logic type, timing constraints and circuit architecture, in contrast to the CMOS logic.
arxiv   +1 more source

VLSI Circuit Optimization for 8051 MCU

open access: yesInternational Journal of Technology, 2018
With the aid of Electronic Design Automation tools, we perform circuit optimization on the 8051 microcontroller. The original 8051 microcontroller operates at a clock frequency 12 MHz, and it was designed based on 3.5-µm process technology.
Kim Ho Yeap   +4 more
doaj   +1 more source

Automatic cable harness layout routing in a customizable 3D environment [PDF]

open access: yes, 2023
Designing cable harnesses can be time-consuming and complex due to many design and manufacturing aspects and rules. Automating the design process can help to fulfil these rules, speed up the process, and optimize the design. To accommodate this, we formulate a harness routing optimization problem to minimize cable lengths, maximize bundling by ...
arxiv   +1 more source

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip [PDF]

open access: yes, 2010
There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores.
Artundo, Iñigo   +4 more
core   +1 more source

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