Results 91 to 100 of about 582,151 (290)
The Effects of Comparator Dynamic Capacitor Mismatch in SAR ADC and Correction
IEEE Access, 2018 This paper proposes a method of correcting the nonlinear parasitic capacitor of the input pair of comparator in successive approximations analog-to-digital converters (SAR ADCs).
Jian Luo +4 more
doaj +1 more source
Empirical Comparison of Chirp and Multitones on Experimental UWB Software Defined Radar Prototype [PDF]
, 2012 This paper proposes and tests an approach for an unbiased study of radar waveforms' performances. Using the ultrawide band software defined radar prototype, the performances of Chirp and Multitones are compared in range profile and detection range.
Denoulet, J. +3 more
core
Reconfiguring the Imaging Pipeline for Computer Vision
, 2017 Advancements in deep learning have ignited an explosion of research on efficient hardware for embedded computer vision. Hardware vision acceleration, however, does not address the cost of capturing and processing the image data that feeds these ...
Buckler, Mark +2 more
core +1 more source
Multi-step capacitor-splitting SAR ADC
Electronics Letters, 2010 A new architecture is proposed which reduces the power consumption and capacitor area in successive approximation register (SAR) analogue-to-digital converters (ADCs). Two identical capacitor-splitting capacitor arrays are used in a two-step process for quantisation, and this significantly reduces the switching power and capacitor area.
J. Lin, W. Yu, G.C. Temes
openaire +1 more source
Two-step split-junction SAR ADC
Electronics Letters, 2010 A new architecture is proposed to reduce the power consumption and capacitor area in successive-approximation register analogue-to-digital converters (SAR ADCs). Two split-junction binary-weighted capacitor arrays are used in a coarse/fine quantisation scheme. This reduces both the power consumption and the capacitor area to a small fraction of that of
W. Yu, J. Lin, G.C. Temes
openaire +1 more source
A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC
IEEE Open Journal of the Solid-State Circuits SocietyThis work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and $4\times $ – $36\times $ lower sampling capacitor
Sumukh Prashant Bhanushali +1 more
doaj +1 more source
Energies, 2018 This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be ...
Behnam Samadpoor Rikan +9 more
doaj +1 more source
Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC. [PDF]
Micromachines (Basel), 2023 Wang YJ, Wang P, Wan LX, Jin Z.
europepmc +1 more source
On the Pulse Intensity Modulation of PSR B0823+26
, 2012 We investigate the radio emission behaviour of PSR B0823+26, a pulsar which is known to undergo pulse nulling, using an 153-d intensive sequence of observations.
A. G. Lyne +59 more
core +1 more source
A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator. [PDF]
Sensors (Basel), 2022 Verma D +7 more
europepmc +1 more source